Quectel Smart LTE Module Series Hardware Design page 64

DSI0_CLK_N
DSI0_CLK_P
DSI0_LN0_N
DSI0_LN0_P
DSI0_LN1_N
DSI0_LN1_P
DSI0_LN2_N
DSI0_LN2_P
DSI0_LN3_N
DSI0_LN3_P
DSI1_CLK_N
DSI1_CLK_P
DSI1_LN0_N
DSI1_LN0_P
DSI1_LN1_N
DSI1_LN1_P
DSI1_LN2_N
DSI1_LN2_P
DSI1_LN3_N
DSI1_LN3_P
The following are the reference designs for LCM interfaces.
SC650T_Hardware_Design
LCD0 MIPI clock signal
116 AO
(negative)
LCD0 MIPI clock signal
115 AO
(positive)
LCD0 MIPI lane 0 data signal
118 AO
(negative)
LCD0 MIPI lane 0 data signal
117 AO
(positive)
LCD0 MIPI lane 1 data signal
120 AO
(negative)
LCD0 MIPI lane 1 data signal
119 AO
(positive)
LCD0 MIPI lane 2 data signal
122 AO
(negative)
LCD0 MIPI lane 2 data signal
121 AO
(positive)
LCD0 MIPI lane 3 data signal
124 AO
(negative)
LCD0 MIPI lane 3 data signal
123 AO
(positive)
LCD1 MIPI clock signal
103 AO
(negative)
LCD1 MIPI clock signal
102 AO
(positive)
LCD1 MIPI lane 0 data signal
105 AO
(negative)
LCD1 MIPI lane 0 data signal
104 AO
(positive)
LCD1 MIPI lane 1 data signal
107 AO
(negative)
LCD1 MIPI lane 1 data signal
106 AO
(positive)
LCD1 MIPI lane 2 data signal
109 AO
(negative)
LCD1 MIPI lane 2 data signal
108 AO
(positive)
LCD1 MIPI lane 3 data signal
111 AO
(negative)
LCD1 MIPI lane 3 data signal
110 AO
(positive)
Smart LTE Module Series
SC650T Hardware Design
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