Quectel Smart LTE Module Series Hardware Design page 32

DSI0_LN1_P 119
DSI0_LN2_N 122
DSI0_LN2_P 121
DSI0_LN3_N 124
DSI0_LN3_P 123
DSI1_CLK_N 103
DSI1_CLK_P 102
DSI1_LN0_N 105
DSI1_LN0_P 104
DSI1_LN1_N 107
DSI1_LN1_P 106
DSI1_LN2_N 109
DSI1_LN2_P 108
DSI1_LN3_N 111
DSI1_LN3_P 110
SC650T_Hardware_Design
LCD0 MIPI lane 1
AO data signal
(positive)
LCD0 MIPI lane 2
AO data signal
(negative)
LCD0 MIPI lane 2
AO data signal
(positive)
LCD0 MIPI lane 3
AO data signal
(negative)
LCD0 MIPI lane 3
AO data signal
(positive)
LCD1 MIPI clock
AO
signal (negative)
LCD1 MIPI clock
AO
signal (positive)
LCD1 MIPI lane 0
AO data signal
(negative)
LCD1 MIPI lane 0
AO data signal
(positive)
LCD1 MIPI lane 1
AO data signal
(negative)
LCD1 MIPI lane 1
AO data signal
(positive)
LCD1 MIPI lane 2
AO data signal
(negative)
LCD1 MIPI lane 2
AO data signal
(positive)
LCD1 MIPI lane 3
AO data signal
(negative)
LCD1 MIPI lane 3
AO data signal
(positive)
Smart LTE Module Series
SC650T Hardware Design
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