Spi Interface - Quectel EG060K Series Hardware Design

NOTE
Transistor circuit solution is not suitable for applications with high baud rates over 460 kbps.

4.4. SPI Interface

The module provides one SPI interface which only supports master mode with a maximum clock
frequency up to 50 MHz.
Table 18: Pin Definition of SPI Interface
Pin Name Pin No.
SPI_MOSI 163
SPI_CLK 164
SPI_MISO 165
SPI_CS 166
The following figure shows a reference design of PCM and SPI interfaces with an external SLIC IC. The
dotted line in Figure 22 means an optional connection since some SLIC ICs need RST while some do
not.
EG060K &EG120K _Series_Hardware_Design
103
VDD_EXT
MCU/ARM
TXD
RXD
10K
VCC_MCU
RTS
CTS
GPIO
EINT
GPIO
GND
Figure 21: Reference Circuit with MOSFETs
I/O Description
DO SPI master output slave input
DO SPI clock
DI SPI master input slave output
DO SPI chip select
4.7K
VDD_EXT
1 nF
10K
1 nF
VDD_EXT
4.7K
LTE-A Module Series
Module
RXD
TXD
RTS
CTS
DTR
RI
DCD
GND
Comment
1.8 V power domain.
Master only.
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