Quectel Smart LTE Module Series Hardware Design page 49

the OTG device is attached: when USB_ID is kept open (high level by default), SC650T is in USB slave
mode; if USB_ID is connected to ground, it is in OTG mode and USB_VBUS is used to supply power for
peripherals with maximum output of 5V/1A.
The following is a reference design for USB interface:
Module
USB_ VBUS
USB_DM
USB_DP
CC1
CC2
USB_SS_TX_P
USB_SS_TX_M
USB_SS_RX_P
USB_SS_RX_M
CC_OUT
In order to ensure USB performance, please follow the following principles while designing USB interface.

It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.

Pay attention to the influence of junction capacitance of ESD protection devices on USB data lines.
Typically, the capacitance value should be less than 2pF for USB 2.0 and less than 0.5pF for USB
3.0.

Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
SC650T_Hardware_Design
Figure 11: USB 2.0 Interface Reference Design
VDD_3V
C1 C14
4.7uF 100nF
Figure 12: USB Type-C Interface Reference Design
C2 A0+ C6
B0+
C3
A0- B0- C7
C4
C8
A1+ B1+
C5 C9
A0- B1-
C10
C0+
SEL
C0- C11
VDD
C12
C1+
PD
C13
C1-
R1
Switch
Smart LTE Module Series
SC650T Hardware Design
USB 3.0
VBUS_ VBUS
D-
D+
CC 1
CC2
TX1+
TX1-
RX1+
RX1-
TX2+
TX2-
RX2+
RX2-
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