Gpio Interfaces - Quectel Smart LTE Module Series Hardware Design

CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines. In PCB design, please
control the characteristic impedance of them as 50Ω, and do not cross them with other traces. It is
recommended to route the trace on the inner layer of PCB, and keep the same trace length for CLK, CMD,
DATA0, DATA1, DATA2 and DATA3. CLK additionally needs ground shielding.
Layout guidelines:

Control impedance as 50Ω± 10%, and ground shielding is required.

The total trace length difference between CLK and other signal line traces should not exceed 1mm.
Table 13: SD Card Signal Trace Length Inside the Module
Pin No. Signal
70 SD_CLK
69 SD_CMD
68 SD_DATA0
67 SD_DATA1
66 SD_DATA2
65 SD_DATA3

3.13. GPIO Interfaces

SC650T has abundant GPIO interfaces with power domain of 1.8V. The pin definition is listed below.
Table 14: Pin Definition of GPIO Interfaces
Pin Name
GPIO_0
GPIO_1
GPIO_2
GPIO_3
SC650T_Hardware_Design
Length (mm)
30.44
31.60
31.50
30.96
32.70
31.62
Pin No. GPIO
248 GPIO_0
247 GPIO_1
201 GPIO_2
200 GPIO_3
Smart LTE Module Series
SC650T Hardware Design
Comment
Default Status
1)
B-PD:nppukp
B-PD:nppukp
B-PD:nppukp
B-PD:nppukp
Comment
2)
Wakeup
55 / 131