Gpio Interfaces - Quectel SC200L-EM Hardware Design

recommended to route the trace on the inner layer of PCB and keep the same trace length for CLK, CMD,
DATA0, DATA1, DATA2 and DATA3. CLK needs separate ground shielding.
Layout guidelines:
 Control impedance to 50Ω ±10% and ground shielding is required.
 The total trace length difference between CLK and other signal line traces like CMD and DATA
should not exceed 1 mm.
Table 13: SD Card Trace Length Inside the Module
Pin No.
39
40
41
42
43
44

3.12. GPIO Interfaces

SC200L has abundant GPIO interfaces with a power domain of 1.85V. The pin definition is listed below.
Table 14: Pin Definition of GPIO Interfaces
Pin Name
GPIO_87
GPIO_86
GPIO_85
GPIO_88
GPIO_139
GPIO_136
SC200L_Hardware_Design
Signal
SD_CLK
SD_CMD
SD_DATA0
SD_DATA1
SD_DATA2
SD_DATA3
Pin No GPIO
33 GPIO_87
90 GPIO_86
97 GPIO_85
98 GPIO_88
99 GPIO_139
100 GPIO_136
SC200L Hardware Design
Length (mm)
43.50
42.82
45.92
46.24
43.97
45.62
Default state Comment
1)
IN/PD
IN/PU
OUT/Hiz
IN/PU
IN/PU
IN/PU
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