Table A-3 Hdrz Signals - ARM Versatile/IT1 User Manual

Generic Tile signal
SPARE[12:4]
SPARE[3:0]
C_TDO_OUT,
C_TDO_IN
C_TDI,
C_TDO_IN
C_TCK
C_TMS
D_TDI, D_TDO
D_TCK, D_RTCK
CLK_GLOBAL
CLK_POS_UP_OUT
CLK_POS_UP_IN
CLK_POS_DN_IN
CLK_POS_DN_OUT
Z[127:0]
Z128
Z129
ARM DUI 0188C
Table A-3 lists the signals on the HDRZ connector and the associated prototyping and
peripheral signal.
Prototyping
pad
T9-T1
S12-S9
-
-
-
-
-
-
X17 (out)
X20 (in)
X16 (enable)
X21
X18
X19
X22
-
A1
A2
Copyright © 2004-2007. ARM Limited. All rights reserved.
Interface Tile signal
SPARE[12:4]
SPARE[3:0]
C_TDO_OUT,
C_TDO_IN
C_TDI,
C_TDO_IN
B_C_TCK
C_TMS
D_TDI, D_TDO
D_TCK, D_RTCK
CLK_GLOBAL_OUT,
CLK_GLOBAL_IN
CLK_POS_UP_IN
EXT_CLK_POS_UP_IN
CLK_POS_UP_OUT
CLK_POS_DN_OUT
CLK_POS_DN_IN
EXT_CLK_POS_DN_IN
-
DAC_CLK
DAC_DIN
Signals and Pinouts

Table A-3 HDRZ signals

Effect of peripheral
enable switches (and
other control signals)
-
-
(to use JTAG, remove
resistor R1 on J1 to remove
short)
(connected if
nTILE_DET is HIGH)
-
-
(connected if
nTILE_DET is HIGH)
(connected if
nTILE_DET is HIGH)
(Interface tile generates
global clock if
CLK_GLOBAL_nEN on
prototyping area is pulled
LOW)
(default)
(selected by LK2)
-
-
(default)
(selected by LK1)
-
-
-
A-5