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Table 2-4. Video Configuration Switch (SW2)
Switch Position (Default)
1 (
)
OFF
2 (
)
OFF
3 (
)
OFF
4 (
)
OFF
5 (
)
OFF
6 (
)
ON
Positions 1 thorough 5 of
control signals of the
FIELD
cessor's PPIs. In standard configuration of the encoder and decoder, this is
not necessary because the processor is capable of reading the embedded
control information, which is in the data stream.
Position 6 of
SW2
ADV7183A. When the switch is "
tions, and the decoder output enable is held "
Boot Mode Switch (SW3)
The
switch positions 1 and 2 set the ADSP-BF561 processor's boot
SW3
mode as described in
boot. When
SW3
Table 2-5. Boot Mode Select Switch (SW3)
Position 1 BMODE0
ON
ON
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Processor Signal
PPI1 SYNC1
PPI0 SYNC1
PPI1 SYNC2
PPI1 SYNC2
(
)
PF3
FIELD
PF2
determine how and if the
SW2
and
PPI0
determines whether
OFF
Table
2-5. Position 3 sets the processor's PLL on
position 3 is "
", the PLL is in bypass.
ON
Position 2 BMODE1
ON
OFF
EZ-KIT Lite Hardware Reference
Video Signal
ADV7179
ADV7183A
ADV7183A
ADV7179
ADV7183A
ADV7183A
interfaces are routed to the pro-
PPI1
connects to the
PF2
",
can be used for other opera-
PF2
" with a pull-up resistor.
HIGH
Boot Mode
Reserved
Flash memory
,
, and
SYNC1
SYNC2
signal of the
~OE
2-11
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