Jtag Emulation Port - Analog Devices ADSP-BF561 EZ-KIT Lite Manual

Table 2-3. Connector Interfaces
Connector Interfaces
5V, G ND, Address, Data,
J1
3.3V, GND, SPI, NMI,
J2
signals
5V, 3.3V, GND, UART,
J3
Limits to the current and to the interface speed must be taken into consid-
eration when you use the expansion interface. The maximum current limit
is dependent on the capabilities of the used regulator. Additional circuitry
can also add extra loading to signals, decreasing their maximum effective
speed.
Analog Devices does not support and is not responsible for the
effects of additional circuitry.

JTAG Emulation Port

The JTAG emulation port allows an emulator to access the processor's
internal and external memory through a 6-pin interface. The JTAG emu-
lation port of the processor also connects to the USB debugging interface.
When an emulator connects to the board at
face is disabled. See
about the JTAG connector.
To learn more about available emulators, contact Analog Devices (see
"Product Information").
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
PPI0 3–0
PPI0 SYNC3–1
, Reset, Video control signals
PPI1 15–0
"JTAG (P4)" on page 2-20
, ,
PF15–6 PF4
, , ,
SPORT0 SPORT1 PF15–0
, the USB debugging inter-
P4
for more information
, EBUI control
2-9