Video Interface - Analog Devices ADSP-BF561 EZ-KIT Lite Manual

The AD1836A codec reset is controlled by the processor's programmable
flag . When
PF15
reset is de-asserted. Note, when
the AD1836A reset is asserted due to the pull-down resistor. See
grammable Flags" on page 2-4
Example programs are included in the EZ-KIT installation direc-
tory to demonstrate the AD1836A codec operation.

Video Interface

The board supports video input and output applications. The ADV7179
video encoder provides up to three output channels of analog video, while
the ADV7183A video decoder provides up to three input channels of ana-
log video. The video encoder connects to the Parallel Peripheral
Interface 1 (
PPI1
Peripheral Interface 0, (
that is configured by the
(SW5)" on page 2-13
Both the encoder and the decoder connect to the Parallel Peripheral Inter-
faces (PPI input clock) of the ADSP-BF561 processor. For additional
information on the video interface hardware, refer to
page 2-6.
For the video interface to be operational, the following basic steps must be
performed.
1. Configure the
to "Video Configuration Switch (SW2)" on page 2-10
2. De-assert the video device's reset by setting a corresponding pro-
grammable flag "
encoder's reset, while
reset.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
is " ", the reset is asserted. When
PF15 0
PF15
for more information.
), while the video decoder connects to the Parallel
). Each PPI interface has an individual clock
PPI0
switch settings. See
SW5
for more information.
DIP switch as required by the application. Refer
SW2
". Note that
High
controls the ADV7183A decoder's
PF13
Using EZ-KIT Lite
is not driven (configured as input),
"PPI Clock Select Switch
"PPI Interfaces" on
controls the ADV7179
PF14
is " ", the
PF15 1
"Pro-
for details.
1-11