Omron SYSMAC mini SP10 Operation Manual
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Omron SYSMAC mini SP10 Operation Manual

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Cat.No. W197–E1–2B
SYSMAC mini
Programmable Controllers
SP10/SP16/SP20
OPERATION MANUAL

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Summary of Contents for Omron SYSMAC mini SP10

  • Page 1 Cat.No. W197–E1–2B SYSMAC mini Programmable Controllers SP10/SP16/SP20 OPERATION MANUAL...
  • Page 2 SYSMAC mini Programmable Controllers SP10/SP16/SP20 Operation Manual Revised September 1997...
  • Page 3 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high–quality products, the information contained in this manual is subject to change without notice.

  • Page 4: Table Of Contents

    TABLE OF CONTENTS PRECAUTIONS ....... . . 1 Intended Audience .
  • Page 5 TABLE OF CONTENTS Appendix A Standard Models ............B Specifications .
  • Page 6 It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of the features of the SP-series PCs and Units that comprise SP-series systems are also provided.

  • Page 7: Precautions

    PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the PC. You must read this section and understand the information contained before attempting to set up or operate a PC system. 1 Intended Audience .

  • Page 8: Intended Audience

    It is extreme important that the PC be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the abovementioned applications.

  • Page 9: Application Precautions

    Application Precautions Application Precautions Observe the following precautions when using the PC. WARNING Failure to abide by the following precautions could lead to serious or possibly fatal injury. Always heed these precautions. • Always ground the system to 100 Ω or less when installing the system to pro- tect against electrical shock.

  • Page 10: Introduction

    SECTION 1 Introduction This section will introduce you to Programmable Controllers in general and specifically to the SP-series PCs and the var- ious Units available for use with them. It also describes the configurations possible with the SP-series PCs and how to connect these configurations.

  • Page 11: Features

    Section 1-2 PC Basics Features Miniature High-performance The SP-series PCs are extremely compact yet have a programming capacity of about 100 instructions in the SP10 or about 240 instructions in the SP16 and SP20. The SP10 is equipped with 34 different instructions and the SP16 and SP20 are equipped with 38 instructions.
  • Page 12 Relay vs. PC Terminology The terminology used throughout this manual is somewhat different from relay terminology, but the concepts are the same. The following table shows the relationship between relay terms and the terms used for OMRON PCs. Relay term PC equivalent...
  • Page 13 Section 1-2 PC Basics There are also output bits in memory that are allocated to output points on Units through which output signals are sent to output devices, i.e., an out- put bit is turned ON to send a signal to an output device through an output point.

  • Page 14: Units

    Section 1-3 Units signing a Control System is thus determining the requirements of the con- trolled system. Once the entire Control System has been designed, the task of program- ming, debugging, and operation as described in the remaining sections of this manual can begin.
  • Page 15 Section 1-3 Units SP16 and SP20 The SP20 is essentially the same as the SP16. The SP16 is shown below. RDM(23) input Power supply (See note 3) Inputs Analog timer 1 setting adjustment Programming Console/ Link Adapter connector Analog timer 2 setting adjustment Power terminals Outputs...
  • Page 16 Section 1-3 Units The Programming Console is used to write and transfer programs to the PC. It is also used to monitor operation and modify data. The Programming Con- sole can be connected directly to the PC for single PCs. It can also be con- nected via a Link Adapter when PCs are connected in a PC Link configura- tion to access each PC individually without reconnection.

  • Page 17: Pc Configuration

    Section 1-4 PC Configuration PC Configuration The SP-series PCs can be configured to control a control system of from 10 through 80 I/O points. An SP10 provides 10 I/O points (6 input and 4 output points), an SP16 provides 16 I/O points (10 input and 6 output points), and an SP20 provides 20 I/O points (12 input and 8 output points).
  • Page 18 Section 1-4 PC Configuration Note 1. When two or more PCs are linked, apply power to all of the PCs at once or to PC #0 last. 2. When using a Link Adapter, one PC must be connected to connector number 0 on the Link Adapter.

  • Page 19: Installation

    SECTION 2 Installation This section provides information on mounting and wiring the CPUs and on I/O specifications. Basic unit connections are described in 1-4 PC Configuration. Detailed specifications are provided in Appendix B Specifications. Dimensions ............. . Installation .

  • Page 20: Dimensions

    Section 2-1 Dimensions Dimensions This section gives mounting dimensions. All dimensions are in millimeters. CPUs SP10-D_-_, SP16-D_-_, SP20-D_-_ PC model Dimension A Dimension B SP10-D_-_ SP16-D_-_ SP20-D_-_ Link Adapter SP10-AL001 Programming Console SP10-PRO01-V1...

  • Page 21: Installation

    Section 2-2 Installation Surface Mounting Dimensions 2-M4 PC model Dimension A SP10-D_-_ SP16-D_-_ SP20-D_-_ Mounting Track The SP-series PCs can be mounted onto DIN Tracks. Model No. Length (L) PFP-50N 50 cm PFP-100N PFP-100N2 PFP-50N/PFP-100N 7.3±0.15 35±0.3 27±0.5 1000 (500) * PFP-100N2 35±0.3 29.2...

  • Page 22: Cooling

    Section 2-2 Installation • An ambient temperature that falls below 0° or exceeds 55°C for the CPU, or that falls below 0°or exceeds 45°C for the Programming Console. • Abrupt changes in temperature that cause condensation. • A relative humidity less than 10% or greater than 90%. •...

  • Page 23: Wiring

    Section 2-3 Wiring Whenever possible, use wiring conduit to hold the I/O wiring. Standard wiring conduit should be used, and it should be long enough to completely contain the I/O wiring and keep it separated from other cables. 2-2-4 Mounting Requirements The system consists of from one to four CPUs and, if more than one CPU is used, a Link Adapter.

  • Page 24: I/O Connections

    Section 2-3 Wiring each PC, firstly to prevent voltage drops caused by surge currents and sec- ondly, to prevent the breaker from malfunctioning. The following diagrams show the proper way to connect the power source to the PC. Refer to Appendix B Specifications for detailed specifications. AC Connections AC Power Source 1:1 Isolation...
  • Page 25 Section 2-3 Wiring 7.5 mm max. 7.5 mm max. Output Circuits Refer to Appendix B Specifications for detailed specifications. Relay Contact Outputs Maximum switching Resistive loads 250 VAC, 2 A (cosf=1), 24 VDC, 2A/pt capacity Inductive loads 250 VAC, 0.5 A (cosf=0.4)/pt Minimum switching capacity 5 VDC, 100 mA Circuit configuration...
  • Page 26 Section 2-3 Wiring The following example uses an SP10 CPU. Loads Loads Load power supply 24 VDC Input Circuits Either positive or negative poles of the power supply can be connected to the common (COM) terminals, enabling connection of both PNP (negative com- mon) and NPN (positive common) inputs.
  • Page 27 Section 2-3 Wiring input devices such as sensors, etc., make sure that the power consumption of the devices does not exceed the ratings of the PC. DC Input Examples The following diagrams show the correct way to wire the terminals on the CPU.

  • Page 28: Programming Console

    Section 2-4 Programming Console turns OFF). Proper operation for power interruptions will not be possible if NC contacts are used in conjunction with counter, shift, or keeping (latching) instructions. 2-3-3 Precautions Unit Sticker A sticker is provided on the upper face of the CPU to prevent foreign objects, such as wire clippings, from entering the CPU.

  • Page 29: Designating The Pc

    Section 2-4 Programming Console Connection to a Link Adaptor SP10-AL001 Link Adaptor SP10-PRO01-V1 Programming Console SP10-CN__1 Connecting Cables SP__ #0 SP__ #1 SP__ #2 SP__ #3 Connecting Cable Use one of the following Connecting Cables to connect the Programming Console. SP10-CN221 (2 m) SP10-CN421 (4 m) Note The sum of the cable lengths between Unit #0 and the Link Adapter and be-...

  • Page 30: Input Filters

    Section 2-4 Programming Console operation mode of the PC being monitored are identical, the following mes- sage is displayed. The number in the top left corner indicates the number of the PC being monitored, in this case PC #1. 1 000 When the mode switch of the Programming Console and the operation mode of the PC being monitored are not identical, the following message is dis- played.
  • Page 31 Section 2-4 Programming Console the PC, as shown in the table below. A different filter value can be set for each group. The filter values can be set in PROGRAM mode only and must be set before operating the PC. The filter values are set simultaneously in the PC and in the Programming Console.
  • Page 32 Section 2-4 Programming Console SP10-PRO01 0 FILTER VAL GROUP 1 1 2 2 Group 2: 5 ms Group 1: 1 ms SP10-PRO01-V1 The display will show the settings for groups 1 and 2 when the Programming Console is connected to an SP10. 0 PC :0 1 PC settings...

  • Page 33: Programming

    SECTION 3 Programming This section takes you all the way through the programming procedure from understanding memory area allocation to debugging and executing the program. Section 4 Operation will then provide procedures for monitoring PC operation and manipulating data after you have written, input, and debugged the program. Introduction .
  • Page 34 Instruction Set ............3-7-1 Notation .

  • Page 35: Introduction

    Section 3-2 Memory Areas Introduction There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix F I/O Assignment Sheets and Appendix G Program Coding Sheet. 1, 2, 3.. 1. Obtain a list of all I/O devices and the I/O points that have been as- signed to them and prepare a table that shows the I/O bit allocated to each I/O device.

  • Page 36: Data Area Structure

    Section 3-2 Memory Areas Area No. of Word Function bits addresses addresses Work bits SP10 0008 to 0015 These bits are used within the program to aid programming. 0104 to 0115 0200 to 0215 SP16 0010 to 0015 0106 to 0115 0200 to 0215 10 to 20 1000 to 2015...
  • Page 37 Section 3-2 Memory Areas Bit number Word 000 Word 001 To designate data by word, all that is necessary is the acronym (if required) and the two-digit word address. To designate data by bit, the word address is combined with the bit number as a single four-digit address. The following table show examples of this.

  • Page 38: I/O Bits

    Section 3-2 Memory Areas to decimal by considering each four bits from the right. Binary 0101 is deci- mal 5; binary 0111 is decimal 7. The decimal equivalent would thus be 5,757. Note that this is not the same numeric value as the hexadecimal equivalent of 0101011101010111, which would be 5,757 hexadecimal, or 22,359 in deci- mal (16 x 5 + 16...

  • Page 39: Work Bits

    Section 3-2 Memory Areas Inputs Outputs Word Terminal Word Terminal 0000 0100 0001 0101 0002 0102 0003 0103 0004 0005 After the program is executed, the status of outputs determined by the pro- gram is actually output from the output bits to the output terminals. Also, the current status of all inputs is read from the input terminals to the input bits.
  • Page 40 Section 3-2 Memory Areas Information in the following table applies to the SP10, SP16, and SP20. Word Function 0300 PC #0 Turns ON when a PC link error occurs. 0301 PC #1 0302 PC #2 0303 PC #3 0304 PC #0 Turns ON when PC link is normal or in RUN mode. 0305 PC #1 0306...

  • Page 41: Lr Area

    Section 3-2 Memory Areas Carry Flag, CY Bit 0312 turns ON when a carry occurs as a result of arithmetic operation. Less Than Flag, LE Bit 0313 turns ON when the result of a comparison operation between two operands shows the first to be less than the second.
  • Page 42 Section 3-2 Memory Areas the LR area. Once this is done, each PC is allocated write bits in the LR area that it can write to so that the other PCs can read the data. All PCs in the link will thus write to certain LR words and read from the words written by the oth- er PCs to transfer data back and forth.
  • Page 43 Section 3-2 Memory Areas LR NUMBER ? 1.0 2.64 3.128 LR NUMBER OK 1.0 2.64 3.128 LR Allocation Read To check the size of the LR Area that has been allocated, use the following key sequence. This procedure can be performed in either RUN or PRO- GRAM mode.

  • Page 44: Dr Area

    Section 3-2 Memory Areas PC #0 PC #1 PC #2 PC #3 LR 00 PC #0 PC #0 PC #0 PC #0 LR 01 LR 02 PC #1 PC #1 PC #1 PC #1 LR 03 LR 04 PC #2 PC #2 PC #2 PC #2...

  • Page 45: The Programming Console

    Section 3-3 The Programming Console and counters. All of these are accessed through TC numbers ranging from TC 00 through TC 15. Each TC number is defined as either a timer or count- er using one of the following instructions: TIM, TIMM(20), TIMH(21), ATIM(22), ATM1(25), ATM2(26), CNT, RDM(23), or CNTH(24).

  • Page 46: The Keyboard

    Section 3-3 The Programming Console tions. The red Clear Key is used to clear the display and cancel Program- ming Console operations. Key functions are described in detail in the next section. 3-3-1 The Keyboard Function Function Key Designates instructions via function codes or designates Programming Console functions.

  • Page 47: Basic Programming

    Section 3-4 Basic Programming 3-3-2 PC Modes There are two PC operating modes that are set from the Programming Con- sole: RUN and PROGRAM. RUN mode is used for normal program execution once the program has been input. In RUN mode, input terminal status is read into the PC and out- put terminals are updated according to program execution results.
  • Page 48 Section 3-4 Basic Programming Basic Ladder Diagram A ladder diagram consists of one line running down the left side with lines branching off to the right. The line on the left is called the bus bar; the branching lines, instruction lines or rungs. (Sometimes a right bus bar is also drawn.) Along the instruction lines are placed conditions that lead to other instructions on the right side.

  • Page 49: Mnemonic Code

    Section 3-4 Basic Programming gram can be determined by I/O status, flag status, status contained in work bits, timer/counter status, etc. Logic Blocks The way that conditions correspond to what instructions is determined by the relationship between the conditions within the instruction lines that connect them.

  • Page 50: Ladder Instructions

    Section 3-4 Basic Programming blank. If the instruction requires no definer or bit operand, the operand col- umn is left blank for first line. It is a good idea to cross through any blank data column spaces (for all instruction words that do not require data) so that the data column can be quickly scanned to see if any addresses have been left out.
  • Page 51 Section 3-4 Basic Programming struction. If either is OFF, the result will also be OFF. The execution condition for the first AND instruction in a series is the first condition on the instruction line. Each AND NOT instruction in a series would take the logical AND between its execution condition and the inverse of its operand bit.

  • Page 52: Output And Output Not

    Section 3-4 Basic Programming used to control the status of the designated operand bit according to the ex- ecution condition. With the OUTPUT instruction, the operand bit will be turned ON as long as the execution condition is ON and will be turned OFF as long as the execution condition is OFF.

  • Page 53: Logic Block Instructions

    Section 3-4 Basic Programming AND LOAD Although simple in appearance, the diagram below requires an AND LOAD instruction. 0000 0002 Address Instruction Operands Instruction 0000 0001 0003 0001 0002 OR NOT 0003 AND LD The two logic blocks are indicated by dotted lines. Studying this example shows that an ON execution condition will be produced when: either of the conditions in the left logic block is ON (i.e., when either bit 0000 or bit 0001 is ON), and when either of the conditions in the right logic block is ON (i.e.,...
  • Page 54 Section 3-4 Basic Programming Address Instruction Operands 0000 0001 Instruction 0000 AND NOT 0001 0002 0003 0002 0003 OR LD Naturally, some diagrams will require both AND LOAD and OR LOAD instruc- tions. Logic Block Instructions in To code diagrams with logic block instructions in series, the diagram must be Series divided into logic blocks.
  • Page 55 Section 3-4 Basic Programming 0000 0001 0002 0003 Address Instruction Operands 0101 0000 AND NOT 0001 0201 0002 0003 0004 0201 0004 Block Block AND LD — 0101 Although the following diagram is similar to the one above, block b in the dia- gram below cannot be coded without separating it into two blocks combined with OR LOAD.
  • Page 56 Section 3-4 Basic Programming ever, OR LOAD must be used to combine the top and bottom blocks on both sides, i.e., to combine a1 and a2; b1 and b2. Block Block Address Instruction Operands 0000 0000 0001 0004 0005 AND NOT 0001 0103 LD NOT...
  • Page 57 Section 3-4 Basic Programming Address Instruction Operands 0002 0003 0000 LR 0000 0002 AND NOT 0003 0001 0001 0000 0004 0005 LD NOT 0004 0106 0107 0005 OR LD LD NOT 0106 0107 OR LD 0000 The following diagram requires five blocks, which here are coded in order before using OR LOAD and AND LOAD to combine them starting from the last two blocks and working backward.

  • Page 58: Coding Multiple Right-Hand Instructions

    Section 3-4 Basic Programming The next and final example may at first appear very complicated but can be coded using only two logic block instructions. The diagram appears as fol- lows: Block a 0000 0001 0002 0003 0004 0005 0100 0010 0011 0106...

  • Page 59: Inputting The Program

    Section 3-5 Inputting the Program on the instruction line. In the following example, the last instruction line con- tains one more condition that corresponds to an AND with bit 0004. 0000 0003 Address Instruction Operands DR 0001 0000 0001 0001 0100 0002 0000...

  • Page 60: Designating The Pc

    Section 3-5 Inputting the Program the PC. To gain access to the system when the “Password!” message ap- pears, press CLR and then MON. Then press CLR to clear the display. If the Programming Console is connected to the PC when PC power is al- ready on, the first display below will indicate the mode the PC was in before the Programming Console was connected.

  • Page 61: Clearing Memory

    Section 3-5 Inputting the Program 1 000 When the mode switch of the Programming Console and the operation mode of the PC being monitored are not identical, a message like the following one will be displayed. <RUN> MODE SET ERR In this example, the message indicates that the Programming Console is set to PRGM (program) mode, and that PC #1 is set to RUN mode.

  • Page 62: Clearing Error Messages

    Section 3-5 Inputting the Program key after entering the function number 60. If not specified for retention, both areas will be cleared. CNT is used for the entire TC area. The display will show those areas that will be cleared. It is also possible to retain a portion of the Program Memory from the first memory address to a specified address.

  • Page 63: Entering Or Editing Programs

    Section 3-5 Inputting the Program Once the address is entered, press the up or down key and the desired con- tents will be displayed. The up and down keys can then be used to scroll through Program Memory. Each time one of these keys is pressed, the next or previous word in Program Memory will be displayed.
  • Page 64 Section 3-5 Inputting the Program To input a program, just follow the mnemonic code that was produced from the ladder diagram, ensuring that the proper address is set before starting. Once the proper address is displayed, input the first instruction word, and input any operands required, pressing ENT after each operand is typed into the Programming Console, i.e., ENT is pressed at the end of each line of the mnemonic code.

  • Page 65: Checking The Program

    Section 3-5 Inputting the Program 0 000 0000 0 001READ NOP (00) 0 001 0 001READ DATA A #0000 0 001 DATA A #0150 0 002READ NOP (00) 0 002 FUN (??) 0 002 TIMH(21) 0 002READ DATA A TIMH(21) #0000 0 002 DATA A...

  • Page 66: Program Transfer

    Section 3-5 Inputting the Program stop and a display indicating the error and the error’s address will appear. Press MON to continue the check. If an error is not found, the program will be checked through to the first END(01). When the check has reached the first END, “PRGM CHK END(01)”...
  • Page 67 Section 3-5 Inputting the Program Programming Console Automatic Download data transfer Program key Upload EEP- input, write, edit, and transfer Compare Memory backup Download Upload Memory Card Note 1. New Memory Cards must be initialized before data can be stored. Be sure to format Memory Cards before use.
  • Page 68 Section 3-5 Inputting the Program Key Sequence Download ProCoAPC Program trans- ferred to PC or to Programming Con- sole. Upload UM+DR PCAProCo DR area data is usually written to the PC directly. Hence, if both the program and the data in the PC is to be transferred, specify UM+DR.

  • Page 69: Program Searches

    Section 3-5 Inputting the Program 3-5-9 Program Searches The program can be searched for occurrences of any data area address or timer/counter used in an instruction. Searches can be performed from any currently displayed address or from a cleared display. Once an occurrence of an instruction or bit address has been found, any ad- ditional occurrences of the same instruction or bit can be found by pressing MON again.
  • Page 70 Section 3-5 Inputting the Program Key Sequences Locate position in program, then enter: Instruction When an instruction is inserted or deleted, all addresses in Program Memory following the operation are adjusted automatically so that there are no blank addresses and no unaddressed instructions. Example The following mnemonic code shows the changes that are achieved in a pro- gram through the key sequences and displays shown below.
  • Page 71 Section 3-5 Inputting the Program Inserting an Instruction 0 000 Find the address prior 0 000CONT SEARCH to the insertion point 0000 0 000CONT SEARCH 0101 Program After Insertion Address Instruction Operands 0 007CONT SEARCH 0000 0101 0001 0001 0 006READ AND NOT 0002 AND NOT...

  • Page 72: Advanced Programming

    Section 3-6 Advanced Programming Advanced Programming 3-6-1 Interlocks When an instruction line branches into two or more lines, it is sometimes necessary to use interlocks to maintain the execution condition that existed at a branching point. This is because instruction lines are executed across to a right-hand instruction before returning to the branching point to execute instructions one a branch line.

  • Page 73: Controlling Bit Status

    Section 3-6 Advanced Programming 0000 IL(02) Address Instruction Operands 0000 0001 Instruction 1 IL(02) 0001 0002 Instruction 2 Instruction 1 0002 ILC(03) Instruction 2 ILC(03) If bit 0000 is ON in the revised version of diagram B, above, the status of bit 0001 and that of bit 0002 would determine the execution conditions for in- structions 1 and 2, respectively.

  • Page 74: Differentiate Up And Differentiate Down

    Section 3-6 Advanced Programming FERENTIATE DOWN, and KEEP instructions. All of these instructions ap- pear as the last instruction in an instruction line and take a bit address for an operand.These instructions (except for OUTPUT and OUTPUT NOT, which have already been introduced) are introduced here because of their impor- tance in most programs.

  • Page 75: Self-Maintaining Bits (Seal)

    Section 3-6 Advanced Programming instruction line, the instruction lines are coded first before the instruction that they control. Address Instruction Operands 0002 0003 0002 S: set input KEEP(12) AND NOT 0003 DR 0000 0004 0004 0005 R: reset input KEEP(12) 0000 0005 3-6-5...
  • Page 76 Section 3-6 Advanced Programming ber of ways in which the work bits can be used. Whenever difficulties arise in programming a control action, consideration should be given to work bits and how they might be used to simplify programming. Work bits are often used with the OUTPUT, OUTPUT NOT, DIFFERENTIATE UP, DIFFERENTIATE DOWN, and KEEP instructions.

  • Page 77: Programming Precautions

    Section 3-6 Advanced Programming scan by DIFU(10). Assuming the other conditions controlling bit 0100 are not keeping it ON, the work bit 0200 will turn bit 0100 ON for one scan only. 0000 Address Instruction Operands DIFU(10) 0200 0000 DIFU(10) 0200 0200 0100...
  • Page 78 Section 3-6 Advanced Programming Instruction Diagram A 0408 Address Instruction Operands Instruction 0408 Instruction Diagram B There are a few exceptions to this rule, including the INTERLOCK CLEAR and step instructions. Each of these instructions is used as the second of a pair of instructions and is controlled by the execution condition of the first of the pair.

  • Page 79: Instruction Set

    Section 3-7 Instruction Set Instruction Set The remainder of this section explains SP-series PC instructions individually. 3-7-1 Notation In the remainder of this manual, all instructions will be referred to by their mnemonics. For example, the OUTPUT instruction will be called OUT; the AND LOAD instruction, AND LD.

  • Page 80: Coding Right-Hand Instructions

    Section 3-7 Instruction Set Abbreviation Name Instruction Execution Error Flag 0311 Carry Flag 0312 Less Than Flag 0313 Equals Flag 0314 Greater Than Flag 0315 ER is the flag most commonly used for monitoring an instruction’s execution. When ER goes ON, it indicates that an error has occurred in attempting to execute the current instruction.
  • Page 81 Section 3-7 Instruction Set bit operand is also placed on the same line as the mnemonic. All other oper- ands are placed on lines after the instruction line, one operand per line and in the same order as they appear in the ladder symbol for the instruction. The address and instruction columns of the mnemonic code table are filled in for the instruction word only.

  • Page 82: Load, Load Not, And, And Not, Or, And Or Not

    Section 3-7 Instruction Set Address Instruction Data 0000 0001 0000 SFT(33) 0002 0001 DR 00 0002 0215 0200 0215 0215 0201 0214 LR 0000 AND NOT 0200 0201 DR 0015 0100 AND NOT 0214 AND NOT 0000 OR LD 0215 SFT(33) 0015 OUT NOT...

  • Page 83: And Load And Or Load

    Section 3-7 Instruction Set Description These six basic instructions correspond to the conditions on a ladder dia- gram. As described in 3-4 Basic Programming, the status of the bits assigned to each instruction determines the execution conditions for all other instruc- tions.

  • Page 84: Differentiate Up And Differentiate Down - Difu(10) And Difd(11)

    Section 3-7 Instruction Set OUTPUT NOT - OUT NOT Ladder Symbol Operand Data Areas B: Bit Output bits, work bits, DR, LR Limitations Any output bit can generally be used in only one instruction that controls its status. Refer to 3-2-2 I/O Bits for details. Description OUT and OUT NOT are used to control the status of the designated bit ac- cording to the execution condition.
  • Page 85 Section 3-7 Instruction Set Whenever executed, DIFD(11) compares its current execution with the pre- vious execution condition. If the previous execution condition is ON and the current one is OFF, DIFD(11) will turn ON the designated bit. If the previous execution condition was OFF and the current execution condition is either ON or OFF, DIFD(11) will either turn the designated bit OFF or leave it OFF.

  • Page 86: Keep - Keep(12)

    Section 3-7 Instruction Set 3-7-9 KEEP - KEEP(12) Ladder Symbol Operand Data Areas B: Bit KEEP(12) Output bits, work bits, DR, LR Limitations Any output bit can generally be used in only one instruction that controls its status. Refer to 3-2-2 I/O Bits for details. Description KEEP(12) is used to maintain the status of the designated bit based on two execution conditions.

  • Page 87: Interlock And Interlock Clear - Il(02) And Ilc(03)

    Section 3-7 Instruction Set Input Unit KEEP(12) NEVER DR 03 Bits used in KEEP are not reset in interlocks. Refer to the 3-7-10 INTER- LOCK and INTERLOCK CLEAR - IL(02) and ILC(03) for details. Example If a DR bit is used, bit status will be retained even during a power interrup- tion.
  • Page 88 Section 3-7 Instruction Set Instruction Treatment OUT and OUT NOT Designated bit turned OFF. TIM, TIMM(20), TIMH(21), ATIM(22), Reset. ATM1(25), and ATM2(26) CNT, RDM(23), and CNTH(24) Frozen and PV maintained. KEEP(12) Bit status maintained. DIFU(10) and DIFD(11) Not executed (see below). All others Not executed.

  • Page 89: End - End(01)

    Section 3-7 Instruction Set Example The following diagram shows IL(02) being used twice with one ILC(03). Address Instruction Operands 0000 IL(02) 0000 IL(02) 0001 TIM 00 0001 #0015 1.5 s 0002 0015 IL(02) 0002 0003 IL(02) CNT 01 0003 0004 0004 #0150 0150...
  • Page 90 Section 3-7 Instruction Set TIMH(21) is a decrementing ON-delay timer instruction which requires an SV, The SV is input to the thousandths of a second. ATIM(22) is a decrementing ON-delay timer with a hardware adjustment for the SV. On the SP16 and SP20, the hardware adjustment is the same for both ATIM(22) and ATM1(25).

  • Page 91: Timer - Tim

    Section 3-7 Instruction Set 3-7-14 TIMER - TIM Definer Values N: TC number Ladder Symbol # (00 through 15) Operand Data Areas SV: Set value (BCD) SP10: # SP16, SP20: I/O, work, DR, LR, # Limitations SV is between 000.0 and 999.9 seconds. The decimal point is not entered. Each TC number can be used as the definer in only one timer or counter in- struction.
  • Page 92 Section 3-7 Instruction Set OFF, the timer will be reset and 0100 will be turned OFF. When 0001 goes ON, TIM 01 is started. Bit 0101 is also turned ON when 0001 goes ON. When 20 seconds have expired, 0101 is turned OFF. This bit will also be turned OFF when TIM 01 is reset, regardless of whether or not SV has ex- pired.
  • Page 93 Section 3-7 Instruction Set 0000 Address Instruction Operands TIM 01 0000 #0050 5.0 s 0100 0000 0050 TIM 02 0100 #0030 3.0 s AND NOT 0000 TIM 01 0030 KEEP(12) 0100 TIM 02 KEEP(12) 0100 0000 0100 5.0 s 3.0 s Example 4: The length of time that a bit is kept ON or OFF can be controlled by combin- One-Shot Bits...

  • Page 94: Timer - Timm(20)

    Section 3-7 Instruction Set TIM 02 0000 Address Instruction Operands TIM 01 0000 #0010 1.0 s AND NOT TIM 01 TIM 02 0010 #0015 1.5 s TIM 01 0103 0015 0103 0000 0103 1.0 s 1.5 s 1.0 s 1.5 s A simpler but less flexible method of creating a flicker bit is to AND one of the dedicated clock pulse bits with the execution condition that is to be ON when the flicker bit is operating.

  • Page 95: High-Speed Timer - Timh(21)

    Section 3-7 Instruction Set Description TIMM(20) operates in the same way as TIM except that TIMM(20) measures in units of 0.01 second. Refer to 3-7-14 TIMER - TIM for operational details and examples. Except for the above, and all aspects of operation are the same. Precautions Timers in interlocked program sections are reset when the execution condi- tion for IL(02) is OFF.

  • Page 96: Analog Timer 1 And 2 - Atm1(25) And Atm2(26)

    Section 3-7 Instruction Set Limitations The SV is determined by a hardware setting (see below) and does not re- quire numeric input with the instruction. The TC number is automatically set to TIM 15 when ATIM(22) is designated and does not need to be input. Description ATIM(22) operates in the same way as TIM and TIMM(20) except that the SV is determined by the hardware analog timer adjustment on the front of the...

  • Page 97: Counter - Cnt

    Section 3-7 Instruction Set Description ATM1(25) and ATM2(26) operate in the same way as TIM and TIMM(20) ex- cept that their SVs are determined by the #1 and #2 analog timer adjust- ments on the front of the CPU. The hardware setting is converted to BCD and stored in dedicated word 08.
  • Page 98 Section 3-7 Instruction Set Description CNT is used to count down from SV when the execution condition on the count pulse, CP, goes from OFF to ON, i.e., the present value (PV) will be decremented by one whenever CNT is executed with an ON execution condi- tion for CP and the execution condition was OFF for the last execution.
  • Page 99 Section 3-7 Instruction Set 0000 0001 Address Instruction Operands CNT 04 0000 0002 #0150 0001 0002 0410 0410 CNT 04 0150 0103 0103 Example 3: Extended Counters that can count past 9,999 can be programmed by using one CNT to Counter count the number of times another CNT has counted to zero from SV.

  • Page 100: Reversible Drum Counter -Rdm(23)

    Section 3-7 Instruction Set reset by its Completion Flag). TIM 01 is also reset by the Completion Flag for CNT 02 so that the extended timer would not start again until CNT 02 was reset by 0001, which serves as the reset for the entire extended timer. Because in this example the SV for TIM 01 is 5.0 seconds and the SV for CNT 02 is 100, the Completion Flag for CNT 02 turns ON when 5 seconds x 100 times, i.e., 500 seconds (or 8 minutes and 20 seconds) have expired.
  • Page 101 Section 3-7 Instruction Set TC 11 through TC 15 should not be used in RDM(23) if they are required for the specific instruction to which they are assigned. Refer to the table on page Description The reversible drum counter is a ring counter with a counting range of 0000 to 9999.

  • Page 102: High-Speed Counter - Cnth(24)

    Section 3-7 Instruction Set Present value 0000 0001 0002 0003 0004 0005 0004 0003 0002 0001 0000 9999 9998 9997 0000 0000 0000 Count input (II) Reset input (RI) Decrement/increment input (DI)) DR 0000 Limits: 0001 to 0002 DR 0001 Limits: 0004 to 0002 3-7-21 HIGH-SPEED COUNTER - CNTH(24)
  • Page 103 Section 3-7 Instruction Set have a duty factor of 1:1, and the reset signal must have an ON time of at least 250 µs, as shown below. Input 0000 µs µs Input 0001 250 µs min. Inputs 0000 and 0001 can be used as normal inputs when CNTH(24) is not used, but the input signals must be 1 kHz max.

  • Page 104: Shift Register - Sft(33)

    Section 3-7 Instruction Set Present value 0000 0001 0002 0003 0149 0000 Count input, CP (0000) Reset input, R (2003) Start input, SI (0002) Completion Flag ON for 1 scan CNT 13 0101 3-7-22 SHIFT REGISTER - SFT(33) Ladder Symbol Operand Data Areas Wd: Shift word SFT(33)
  • Page 105 Section 3-7 Instruction Set 0005 Address Instruction Operands SFT(33) 0005 0308 0308 DR 10 0008 0008 SFT(33) DR 10 Example 2: The following program controls the conveyor line shown below so that faulty Control Action products detected at the sensor are pushed down a chute. To do this, the execution condition determined by inputs from the first sensor (0001) are stored in a shift register: ON for good products;...

  • Page 106: Move - Mov(30)

    Section 3-7 Instruction Set 3-7-23 MOVE - MOV(30) Ladder Symbol Operand Data Areas S: Source word MOV(30) I/O, work, dedicated (03 only), DR, LR, TC, # D: Destination word Output bits, work bits, DR, LR Description When the execution condition is OFF, MOV(30) is not executed. When the execution condition is ON, MOV(30) copies the content of S to D.

  • Page 107: Compare - Cmp(32)

    Section 3-7 Instruction Set 3-7-25 COMPARE - CMP(32) Ladder Symbol Operand Data Areas Cp1: First compare word CMP(32) I/O, work, dedicated (03 only), DR, LR, TC, # Cp2: Second compare word I/O, work, dedicated (03 only), DR, LR, TC, # Limitations When comparing a value to the PV of a timer or counter, the value must be in BCD.
  • Page 108 Section 3-7 Instruction Set programming, 0100, 0101, and 0102 are changed only when CMP(32) is ex- ecuted. 0000 IL(02) CMP(32) DR 09 0315 0100 Greater Than 0314 0101 Equal 0313 0102 Less Than ILC(03) Address Instruction Operands Address Instruction Operands 0000 0100 IL(02)

  • Page 109: Block Compare - Bcmp(34)

    Section 3-7 Instruction Set Address Instruction Operands Address Instruction Operands 0000 CMP(32) IL(02) 3000 5000 0313 CMP(32) 0101 ILC(03) 4000 0313 0103 0100 3-7-26 BLOCK COMPARE - BCMP(34) SP16 and SP20 Only Ladder Symbol Operand Data Areas CD: Compare data BCMP(34) I/O, work, dedicated (03 only), DR, LR, TC, # CB: First comparison block word...

  • Page 110: Clear Carry - Clc(44)

    Section 3-7 Instruction Set If the content of CB or the table data are changed during execution, execu- tion will continue with the new values. Indirectly addressed DM word is non-existent. (Content of *DM word Flags is not BCD, or the DM area boundary has been exceeded.) Example The following example shows the comparisons made and the results pro- vided for BCMP(34).

  • Page 111: Bcd Subtract - Sub(41)

    Section 3-7 Instruction Set Au + Ad + CY Flags Au and/or Ad is not BCD. Indirectly addressed DR word is non-existent. (Content of *DR word is not BCD, or the DR area boundary has been exceeded.) ON when there is a carry in the result. ON when the result is 0.
  • Page 112 Section 3-7 Instruction Set Caution Caution Be sure to clear the carry flag with CLC(44) before executing SUB(41) if its pre- vious status is not required, and check the status of CY after doing a subtraction with SUB(41). If CY is ON as a result of executing SUB(41) (i.e., if the result is negative), the result is output as the 10’s complement of the true answer.

  • Page 113: And Word- Andw(42)

    Section 3-7 Instruction Set DR 10 9989 (0089 + (10,000 – 0100)) (negative result) Second Subtraction 0000 DR 10 –9989 –0 DR 10 0011 (0000 + (10,000 – 9989)) (negative result) In the above case, the program would turn ON DR 1100 to indicate that the value held in DR 10 is negative.

  • Page 114: Step Define And Step Start-Step(04)/Snxt(05)

    Section 3-7 Instruction Set Description When the execution condition is OFF, ORW(43) is not executed. When the execution condition is ON, ORW(43) logically OR’s the contents of I1 and I2 bit-by-bit and places the result in R. Example Indirectly addressed DR word is non-existent. (Content of *DR word Flags is not BCD, or the DR area boundary has been exceeded.) ON when the result is 0.
  • Page 115 Section 3-7 Instruction Set operand bits in the step are turned OFF and all timers in the step are reset to their SVs. Counters, shift registers, and bits used in KEEP(12) maintain sta- tus. Two simple steps are shown below. 0000 Starts step execution SNXT(05) 0200...
  • Page 116 Section 3-7 Instruction Set 0000 Start SNXT(05) 0200 0200 STEP(04) 0200 0210 CNT 1 0411 0411 #0003 1 Scan Address Instruction Operands Address Instruction Operands 0000 0411 SNXT(05) 0200 STEP(04) 0200 0003 0210...

  • Page 117: Debugging

    Section 3-8 Debugging Debugging After inputting a program and correcting it for syntax errors, it must be ex- ecuted and all execution errors must be eliminated. Execution errors include an excessively long scan and inappropriate control actions, i.e., the program not doing what it is designed to do.

  • Page 118: Program Execution

    Section 3-9 Program Execution 3-8-2 Reading the Scan Time The following operation can be used to read the present scan time and the maximum scan time. The Monitor Key can be pressed consecutively to re- peat the operation. The PC must be in RUN mode. This operation is supported only by the SP16 and SP20.

  • Page 119: I/O Response Time

    Section 3-10 I/O Response Time • After power application, there is a 2.5-s delay Power application before the start of initialization. • Transfer the program from EEPROM to RAM. • Initialization on power-up Resets data areas (except DR area), resets all timers, and checks the link status.

  • Page 120: Single Pcs

    Section 3-10 I/O Response Time 3-10-1 Single PCs Both input and output refreshes are performed at the same time in the CPU cycle, after the program process has been completed. The following section show how the maximum and minimum I/O response times may be calcu- lated.

  • Page 121: Multiple Pcs

    Section 3-10 I/O Response Time input delay Execu- PC Process tion Scan time output delay = Maximum I/O response time = input delay + filter time + (scan time x 2) + output delay = C + (B + 0.5 ms) + ((300 µs + program execution time) x 2) + A 3-10-2 Multiple PCs If more than one PC is linked via a Link Adapter in a distributed control sys-...

  • Page 122: Operation

    SECTION 4 Operation This section describes how to monitor and maintain PC operation once a program has been input and transferred. It also provides the procedure for initializing memory cards. Refer to 3-5-8 Program Transfer for the procedures for transferring programs and data between the Programming Console and the PC or Memory Cards.

  • Page 123: Monitoring Operation And Modifying Data

    Section 4-1 Monitoring Operation and Modifying Data Monitoring Operation and Modifying Data The simplest form of operation monitoring is to display the address whose operand bit status is to be monitored using the Program Read or the search operation. As long as the operation is performed in RUN mode, the status of any bit displayed will be indicated.

  • Page 124: Monitoring Operation And Modifying Data

    Section 4-1 Monitoring Operation and Modifying Data Bit/Word Monitor Key Sequence Program Read [Bit address] Clears leftmost address Cancels monitor operation Shifts to word monitor Multibit/Word Monitor Key Sequence [Bit Address] Scrolls the dis- play Cancels one bit Cancels all monitoring...
  • Page 125 Section 4-1 Monitoring Operation and Modifying Data Examples The following examples show various applications of this monitor operation. Program Read then Monitor 0 001 0 001READ 0 T 00 1234 0 T 01 !0000 Indicates Completion flag is ON 0 001 Monitor operation is cancelled Bit Monitor...

  • Page 126: Force Set/Reset

    Section 4-1 Monitoring Operation and Modifying Data Multi-address Monitoring 0 000 0 000 0 T 00 0100 0 0000 T 00 0100 0 0001 T 00 0100 0 0001 T 00 ^OFF 0100 0 cD00 0001 T 00 10FF ^OFF 0100 0 cD00 0001 T 00 10FF ^OFF 0100 0 T 00 cD00 0001...

  • Page 127: Hexadecimal/Bcd Data Modification

    Section 4-1 Monitoring Operation and Modifying Data Example The following example shows how either bits or counters can be controlled with the Force Set/Reset operation. The displays shown below are for the following program section. Address Instruction Operands 0000 0000 CNT 05 0200 0200...
  • Page 128 Section 4-1 Monitoring Operation and Modifying Data Key Sequence Word currently monitored on [ Data ] left of display. Example The following example shows the effects of changing the PV of a timer. This example is in RUN mode 0 000 0 000 0 T 00 0122...

  • Page 129: Binary Monitor

    Section 4-1 Monitoring Operation and Modifying Data Key Sequence Scrolls the [Word Address] address Binary Monitor clear All monitor clear Example 0 000 0 000 CHANNEL 0 000 CHANNEL 0 cD10 0008 cD10 MON 0000000000000111 0 cD10 0008 0 000 CHANNEL 4-1-5 Binary Data Modification...

  • Page 130: Memory Card Initialization

    Section 4-2 Memory Card Initialization Example 0 000 0 000 CHANNEL 0 000 CHANNEL cD01 MON 0000010101010101 cD01 CHG? 000010101010101 cD01 CHG? 1 00010101010101 cD01 CHG? 10 0010101010101 cD01 CHG? 100 010101010101 cD01 CHG? 1000 10101010101 cD01 CHG? 100 010101010101 cD01 CHG? 10 0010101010101...

  • Page 131: Memory Card Initialization

    Section 4-2 Memory Card Initialization Pressing ENT for the first time, the Programming Console displays the speci- fications of the Memory Card. By pressing ENT again the Programming Con- sole commences formatting the Memory Card. While the card is being for- matted, cursors on the display indicate the progress of the format operation.
  • Page 132 Section 4-2 Memory Card Initialization Error Messages A number of errors relating to the Memory Card may occur during the pro- gram check. If one of the following errors is shown on the display, program transfer cannot proceed. Error Message Meaning/Correction NO END END instruction cannot be found.

  • Page 133: Troubleshooting

    SECTION 5 Troubleshooting Alarm Indicators ............Reading and Clearing Errors and Messages .

  • Page 134: Alarm Indicators

    Section 5-3 Error Messages Alarm Indicators There are three indicators on the front of the CPU that provide visual indica- tion of errors in the PC. The power indicator (POWER) indicates errors due to incorrect application of power to the PC; the error indicator (ERROR) indi- cates fatal errors (i.e., ones that will stop PC operation);...

  • Page 135: Error Flags

    Section 5-4 Error Flags Error Messages The following error messages may appear when inputting a program. Correct the error as indicated and continue with the input operation. Error Message Error Type Possible Cause/Correction PRGM OVER Program too Program size exceeds the capacity. (The last large address is not a NOP instruction, so the program cannot be written.)

  • Page 136: A Standard Models

    Appendix A Standard Models Name Specifications Model number SP10 PC 6 inputs (DC; one common) 100 to 240 VAC Relay outputs SP10-DR-A 4 outputs Transistor outputs SP10-DT-A (2 commons, 2 pts each) 24 VDC Relay outputs SP10-DR-D Transistor outputs SP10-DT-D SP16 PC 10 inputs 100 to 240 VAC Relay outputs...
  • Page 137 Appendix A Standard Models Name Specifications Model number Simulation Board with 6 switches and AC power cord (power switch also included) SP10-ETL01 Switchboard SP16-ETL01 SP20-ETL01 *Note: The cables between CPUs and the Link Adapter must be 4 m or less. The sum of the distance be- tween CPU #0 and the Link Adapter and the distance between the Link Adapter and the Program- ming Console must be 4.2 m or less.

  • Page 138: B Specifications

    Appendix B Specifications General Ratings Item SP__-D_-A SP__-D_-D* Power supply voltage 100 to 240 VAC, 50/60 Hz 24 VDC Operating voltage range 85 to 264 VAC 20.4 to 26.4 VAC Power consumption 30 VA max. 10 W max. 0.1 A max. at 24 VDC ±10% 24-VDC output terminal SP10 None...
  • Page 139 Appendix B Specifications Output Specifications Item Relays Transistors +10% Switching capacity Resistive loads: 2 A, 250 VAC 0.3 A, 24 VDC –15% (cosf=1); 2 A, 24 VDC; 4 A/common Inductive loads: 0.5 A, 250 VAC (cosf=0.4) ON: 10 µs max. ON: 20 µs max.

  • Page 140: C Programming Instructions And Execution Times

    Appendix C Programming Instructions and Execution Times In the operand column, I refers to input bits, O to output bits, W to work bits, D to bits in the designated area, LR to Link Relay bits, DR to Data Retention bits, and TC to timer and counter Completion Flags and PVs. Re- fer to 3-2 Memory Areas for details on bit and word designation.
  • Page 141 Appendix C Instruction Set and Execution Times Name/ Symbol Key inputs Description Operands* mnemonic OUTPUT Specifies an output bit that is to be turned OFF for an ON execution condition and ON for an OFF condition. Bit address OUT NOT TIMER Creates a 0.1-s decrementing timer that starts from the SP10...
  • Page 142 Appendix C Instruction Set and Execution Times Name/ Symbol Key inputs Description Operands* mnemonic DIFFERENTI- Turns ON the designated bit for one scan only on the DIFU(10)B ATE UP rising edge of the execution condition (input signal). Bit address DIFU(10) Used when an operation is to be performed only once each time a signal turns ON.
  • Page 143 Appendix C Instruction Set and Execution Times Name/ Symbol Key inputs Description Operands* mnemonic MOVE NOT Moves the inverse content of a specified word or a MVN(31) MVN(31) specified constant to a destination word. The Equals Flag will turn ON when 0 is moved. COMPARE Compares the contents of two words or constants and Cp1./Cp2:...
  • Page 144 Appendix C Instruction Set and Execution Times Name/ Symbol Key inputs Description Operands* mnemonic LOGICAL OR Performs an OR between two words one bit at a time I1/I2: ORW(43) ORW(43) and places the result in the result word (R). CLEAR Resets the Carry Flag (bit 0312) to 0.
  • Page 145 Appendix C Instruction Set and Execution Times Instruction Execution Times The execution time is given in microseconds. “Word” indicates any data area address except for indirectly ad- dressed DR (*DR). Instruction Number of words ON execution time Conditions OFF execution time I/O, work, or DR, LR, or I/O, work, or...
  • Page 146 Appendix C Instruction Set and Execution Times Instruction Number of words ON execution time Conditions OFF execution time I/O, work, or DR, LR, or I/O, work, or LR, DR, or dedicated TC (see dedicated note) CNTH(24) R: 51.3 39.9 Constant for SV (SP16, SP20) IL: 4.7 49.4...

  • Page 147: D Programming Console Operations

    Appendix D Programming Console Operations If the display is not cleared to all zeros when the CLR Key is pressed at the beginning of a Programming Con- sole operation, continue pressing the CLR Key until the display shows all zeros. Name Modes Basic key sequences...
  • Page 148 Appendix D Programming Console Operations Name Modes Basic key sequences Page LR Alloca- RUN or Used to read the number of LR bits that have been allocated. tion Read PRGM When performed with the SP10-PRO01-V1, both the PC and Programming Console settings are displayed. Bit Search RUN or Used to search the program for...
  • Page 149 Appendix D Programming Console Operations Name Modes Basic key sequences Page Filter Value PRGM Used to adjust the input read filter time. Group 1 Group 2 Group 3 Designation only Each group can be set to 0 ms, 1 ms, SP10 0 to 2 3 to 5...

  • Page 150: E Error And Arithmetic Flag Operation

    Appendix E Error and Arithmetic Flag Operation The following table shows the instructions that affect the ER, CY, GT, LT and EQ flags. In general, ER indi- cates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same.

  • Page 151: F I/O Assignment Sheets

    Appendix F I/O Assignment Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments, as well as details of work bits, data storage areas, timers, and counters. Note Some bits appear as both I/O bits and work bits so that the I/O assignment sheets can be used for any of the SP-series PCs.
  • Page 152 I/O Bits Appendix F I/O Assignment Sheets No.: System: Program: Programmer: Date: Unit #0 Inputs Outputs Field device Notes Field device Notes 0000 0100 0001 0101 0002 0102 0003 0103 0004 0104 0005 0105 0006 0106 0007 0107 0008 0009 0010 0011 Unit #1...
  • Page 153 I/O Bits Appendix F I/O Assignment Records Sheets No.: System: Program: Programmer: Date: Unit #2 Inputs Outputs Field device Notes Field device Notes 0000 0100 0001 0101 0002 0102 0003 0103 0004 0104 0005 0105 0006 0106 0007 0107 0008 0009 0010 0011...
  • Page 154 TC Area and Work Bits Appendix F I/O Assignment Sheets No.: System: Programmer: Program: Date: Unit #: Timers and Counters Word 01 Usage Notes Address T or C Set value Notes 0104 0105 0106 0107 0108 0109 0110 0111 0112 0113 0114 0115...
  • Page 155 TC Area and Work Bits Appendix F I/O Assignment Records Sheets Word: Word: Usage Notes Usage Notes Word: Word: Usage Notes Usage Notes...
  • Page 156 Data Storage Appendix F I/O Assignment Sheets No.: System: Programmer: Program: Date: Unit #: Word Contents Notes Word Contents Notes...

  • Page 157: G Program Coding Sheet

    Appendix G Program Coding Sheet The following pages can be copied for use in coding ladder diagram programs. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands. These will be necessary when inputting programs though a Programming Console or other Pe- ripheral Device.
  • Page 158 Appendix G Program Coding Sheet No.: System: Page 1 Program: Programmer: Date: Address Instruction Operand(s) Address Instruction Operand(s)
  • Page 159 Appendix G Program Coding Sheet No.: System: Page 2 Program: Programmer: Date: Address Instruction Operand(s) Address Instruction Operand(s)
  • Page 160 Appendix G Program Coding Sheet No.: System: Page 3 Program: Programmer: Date: Address Instruction Operand(s) Address Instruction Operand(s)
  • Page 161 Appendix G Program Coding Sheet No.: System: Page 4 Program: Programmer: Date: Address Instruction Operand(s) Address Instruction Operand(s)
  • Page 162 Appendix G Program Coding Sheet No.: System: Page 5 Program: Programmer: Date: Address Instruction Operand(s) Address Instruction Operand(s)

  • Page 163: Glossary

    Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designates the word and/or bit location. For the UM area, an address designates the instruction location (UM area).
  • Page 164 Glossary clock pulse bit A bit in memory that supplies a pulse that can be used to time operations. Various clock pulse bits are available with different pulse widths, and there- fore different frequencies. common data Data that is stored in the LR Area of a PC and which is shared by other PCs in the same the same system.
  • Page 165 Glossary decrement Decreasing a numeric value. default A value automatically set by the PC when the user omits to set a specific val- ue. Many devices will assume such default conditions upon the application of power. delay In tracing, a value that specifies where tracing is to begin in relationship to the trigger.
  • Page 166 Glossary flicker bit A bit that is programmed to turn ON and OFF at a specific frequency. force reset The process of forcibly turning OFF a bit via a programming device. Bits are usually turned OFF as a result of program execution. force set The process of forcibly turning ON a bit via a programming device.
  • Page 167 Glossary instruction line A group of conditions that lie together on the same horizontal line of a ladder diagram. Instruction lines can branch apart or join together to form instruction blocks. interlock A programming method used to treat a number of instructions as a group so that the entire group can be reset together when individual execution is not required.
  • Page 168 Glossary all the same-numbered bits in the two words and output the result to the bit of the same number in the specified result word. memory area Any of the areas in the PC used to hold data or programs. mnemonic code A form of a ladder-diagram program that consists of a sequential list of the instructions without using a ladder diagram.
  • Page 169 Glossary used or as an address to express the location in memory of the data to be used. operand bit A bit designated as an operand for an instruction. operand word A word designated as an operand for an instruction. operating error An error that occurs during actual PC operation as opposed to an initializa- tion error, which occurs before actual operations can begin.
  • Page 170 Glossary Programmable Controller A computerized device that can accept inputs from external devices and gen- erate outputs to external devices according to a program held in memory. Programmable Controllers are used to automate control of external devices. Although single-component Programmable Controllers are available, build- ing-block Programmable Controllers are constructed from separate compo- nents.
  • Page 171 Glossary scan time The time required for a single scan of the ladder-diagram program. self diagnosis A process whereby the system checks its own operation and generates a warning or error if an abnormality is discovered. self-maintaining bit A bit that is programmed to maintain either an OFF or ON status until set or reset by specified conditions.
  • Page 172 Glossary timer A location in memory accessed through a TC bit and used to time down from the timer’s set value. Timers are turned ON and reset according to their execution conditions. transfer The process of moving data from one location to another within the PC, or between the PC and external devices.

  • Page 173: Index

    Index dedicated bit, definition, 31 definers, definition, 71 addressing, nomenclature, 28 digit numbers, 29 analog timers, set value, 33 dimensions arithmetic flags, 71 DIN Track, 13 for mounting, 13 Link Adapter, 12 PC, 12 Programming Console, 12 backup, program and data, 58–70 DIN Track connecting Units, 15 converting, 29...
  • Page 174 Index instructions designation function codes, 56 table, 135 I/O bit, definition, 30 terminology, 39 I/O response times, 111 interlocks, 79–108 I/O wiring diagrams, 16, 17, 18, 19 converting to mnemonic code, 80 indirect addressing, 30, 72 using self-maintaining bits, 67 input bit, definition, 3 input device, definition, 3 input devices, 19...
  • Page 175 Index programming backup onto Memory Cards, 58–63 checks for syntax, 57–58 displaying and clearing error messages, 109 normally closed condition, definition, 40 entering and editing, 55 NOT, definition, 40 example, using shift register, 97 inserting and deleting instructions, 61–64 operand bit, 41 precautions, 69 operands, 39, 71 program transfer to PC, 58...

  • Page 176: Revision History

    Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W197-E1-2B Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.

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