Omron SYSMAC mini SP10 Operation Manual page 141

Instruction Set and Execution Times
Name/ Symbol
mnemonic
OUTPUT
NOT
OUT NOT
TIMER
TIM
COUNTER
CNT
NO
None
OPERATION
NOP(00)
Special Instructions
Name/ Symbol
mnemonic
END
END(01)
INTERLOCK
IL(02)
INTERLOCK
CLEAR
ILC(03)
STEP
DEFINE
STEP(04)
STEP START
SNXT(05)
136
Key inputs
Specifies an output bit that is to be turned OFF for an
OUT NOT
ON execution condition and ON for an OFF condition.
Bit address
ENT
Creates a 0.1-s decrementing timer that starts from the
TIM
TC number
TIM
set value (SV) when the execution condition turns ON.
SV can be between 0.0 and 999.9 s. When the SV has
ENT SV
been timed out, the Completion Flag is turned ON.
ENT
Counts down the number of times the input condition
CP TC number
CNT
turns ON. Each time the input condition turns ON, the
CNT
R
SV
ENT present value (PV) is reduced by 1 and when the count
reaches 0, the Completion Flag (accessed through the
ENT
counter number) turns ON. The SV can be between 0
and 9999.
Does nothing. Can be inserted into a program before
FUN 0 0 ENT
or after modifications are made to prevent program
addresses from changing.
Key inputs
Indicates the end of the program. A program will not be
END(01)
FUN 0 1 ENT
executed unless the END instruction is used.
INTERLOCK and INTERLOCK CLEAR are combined
IL(02)
to control the status of multiple outputs based on the
FUN 0 2 ENT
execution condition of INTERLOCK, and are generally
used to prevent specific bits from being ON
ILC(03)
FUN 0 3 ENT
simultaneously.
Divides a program into sections called steps that can
STEP(04)
FUN 0 4
be executed as separate processes. Up to five steps
Bit address ENT can be created.
STEP(04)B
Turns OFF any previous steps and starts the designated
SNXT(05)
FUN 0 5
step.
ENT
Bit address
Description
Description
Defining the Beginning of a Step (Operand Required)
Ending Step Execution (No Operand)
Appendix C
Operands*
B:
O
W
LR
DR
SP10
N:
TC
SP16, SP20
N:
TC
SP10
N:
TC
SP16, SP20
N:
TC
Operands*
B:
O
W
LR
DR
STEP(04) B
STEP(04)
B:
O
W
LR
DR
SV:
#
SV:
I/O
W
LR
DR
#
SV:
#
SV:
I/O
W
LR
DR
#
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