Controlling Bit Status - Omron SYSMAC mini SP10 Operation Manual

Advanced Programming
0000
0001
0002
0003 0004
0005
0008
3-6-2

Controlling Bit Status

0000
0001
0002
If bit 0000 is ON in the revised version of diagram B, above, the status of bit
0001 and that of bit 0002 would determine the execution conditions for in-
structions 1 and 2, respectively. Because bit 0000 is ON (otherwise the inter-
locked section would not be executed), this would produce the same results
as ANDing the status of each of these bits. If bit 0000 is OFF, the INTER-
LOCK instruction would produce an OFF execution condition for instructions
1 and 2 and then execution would continue with the instruction line following
the INTERLOCK CLEAR instruction.
As shown in the following diagram, more than one INTERLOCK instruction
can be used within one instruction block; each is effective through the next
INTERLOCK CLEAR instruction (i.e., you can have two or more INTERLOCK
instructions without an INTERLOCK CLEAR instruction between them, but
two or more INTERLOCK CLEAR instructions without an INTERLOCK in-
struction between them is meaningless).
If bit 0000 in the above diagram is OFF (i.e., if the execution condition for the
first INTERLOCK instruction is OFF), the section of the program from instruc-
tion 1 through 4 would be interlocked and execution would move to the in-
struction following the INTERLOCK CLEAR instruction. If bit 0000 is ON, the
status of bit 0001 would be loaded as the execution condition for instruction 1
and then the status of bit 0002 would be loaded to form the execution condi-
tion for the second INTERLOCK instruction. If bit 0002 is OFF, the section
from instruction 2 through 4 would be interlocked. If bit 0002 is ON, bit 0003,
bit 0005, and bit 0008 would determine the first execution condition for the
next instruction lines and execution would continue normally.
Note STEP(04) and SNXT(05) cannot be used between the INTERLOCK and IN-
TERLOCK CLEAR instructions.
There are five instructions that can be used generally to control individual bit
status. These are the OUTPUT, OUTPUT NOT, DIFFERENTIATE UP, DIF-
IL(02)
Address Instruction
000 LD
Instruction 1 001 IL(02)
002 LD
Instruction 2
003 Instruction 1
004 LD
ILC(03)
005 Instruction 2
006 ILC(03)
IL(02)
Address Instruction
000
Instruction 1
001
002
003
IL(02)
004
005
Instruction 2
006
007
Instruction 3
008
009
Instruction 4
010
011
ILC(03)
012
013
Section 3-6
Operands
0000
---
0001
0002
---
Operands
LD 0000
IL(02)
LD 0001
Instruction 1
LD 0002
IL(02)
LD 0003
AND NOT 0004
Instruction 2
LD 0005
Instruction 3
LD 0008
Instruction 4
ILC(03)
---
---
---
65