Ladder Instructions - Omron SYSMAC mini SP10 Operation Manual

Basic Programming
3-4-3

Ladder Instructions

LOAD and LOAD NOT
AND and AND NOT
0000
42
blank. If the instruction requires no definer or bit operand, the operand col-
umn is left blank for first line. It is a good idea to cross through any blank
data column spaces (for all instruction words that do not require data) so that
the data column can be quickly scanned to see if any addresses have been
left out.
When programming, addresses are automatically displayed and do not have
to be input unless for some reason a different location is desired for the in-
struction. When converting to mnemonic code, it is best to start at Program
Memory address 000 unless there is a specific reason for starting elsewhere.
Ladder instructions are those instructions that correspond to the conditions
on the ladder diagram. Ladder instructions, either independently or in combi-
nation with the logic block instructions described next, form the execution
conditions upon which the execution of all other instructions are based.
The first condition that starts any logic block within a ladder diagram corre-
sponds to a LOAD or LOAD NOT instruction. Each of these instructions re-
quires one line of mnemonic code. "Instruction" is used as a dummy instruc-
tion in the following examples and could be any of the right-hand instructions
described later in this manual.
0000
A LOAD instruction.
0000
A LOAD NOT instruction.
When this is the only condition on the instruction line, the execution condition
for the instruction at the right is ON when the condition is ON. For the LOAD
instruction (i.e., a normally open condition), the execution condition would be
ON when bit 0000 was ON; for the LOAD NOT instruction (i.e., a normally
closed condition), it would be ON when bit 0000 was OFF.
When two or more conditions lie in series on the same instruction line, the
first one corresponds to a LOAD or LOAD NOT instruction; and the rest of
the conditions, to AND or AND NOT instructions. The following example
shows three conditions which correspond in order from the left to a LOAD, an
AND NOT, and an AND instruction. Again, each of these instructions requires
one line of mnemonic code.
0100 LR 0000
The instruction would have an ON execution condition only when all three
conditions are ON, i.e., when bit 0000 was ON, bit 0100 was OFF, and LR
0000 was ON.
AND instructions in series can be considered individually, with each taking
the logical AND of the execution condition (i.e., the total of all conditions up
to that point) and the status of the AND instruction's operand bit. If both of
these are ON, an ON execution condition will be produced for the next in-
Address Instruction
000
001
002
003
Address Instruction
Instruction
000 LD
001 AND NOT
002 AND
003 Instruction
Section 3-4
Operands
LD 0000
Instruction
LD NOT 0000
Instruction
Operands
0000
0100
LR 0000