Renesas SH7124 R5F7124 Manuals

Manuals and User Guides for Renesas SH7124 R5F7124. We have 1 Renesas SH7124 R5F7124 manual available for free PDF download: Hardware Manual

Renesas SH7124 R5F7124 Hardware Manual (782 pages)

SH7125 series, SH7124 series Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Brand: Renesas | Category: Computer Hardware | Size: 4.9 MB

General Precautions on Handling of Product
4
Preface
6
Table of Contents
9
Section 1 Overview
21
Features of SH7125 and SH7124
21
Block Diagram
26
Pin Assignments
27
Manual
30
Pin Functions
31
Section 2 CPU
37
Features
37
Index
37
Register Configuration
38
General Registers (Rn)
39
Control Registers
39
System Registers
41
Initial Values of Registers
41
Data Formats
42
Register Data Format
42
Memory Data Formats
42
Immediate Data Formats
43
Features of Instructions
43
RISC Type
43
Addressing Modes
46
Instruction Formats
49
Instruction Set
53
Instruction Set by Type
53
Data Transfer Instructions
57
Arithmetic Operation Instructions
59
Logic Operation Instructions
61
Shift Instructions
62
Branch Instructions
63
System Control Instructions
64
Processing States
66
Section 3 MCU Operating Modes
69
Selection of Operating Modes
69
Input/Output Pins
70
Operating Modes
70
Mode 3 (Single Chip Mode)
70
Address Map
71
Initial State in this LSI
74
Note on Changing Operating Mode
74
Section 4 Clock Pulse Generator (CPG)
75
Features
75
Input/Output Pins
78
Clock Operating Mode
79
Register Descriptions
81
Frequency Control Register (FRQCR)
81
Oscillation Stop Detection Control Register (OSCCR)
84
Changing Frequency
85
Oscillator
86
Connecting Crystal Resonator
86
External Clock Input Method
87
Function for Detecting Oscillator Stop
88
Usage Notes
89
Note on Crystal Resonator
89
Notes on Board Design
89
Section 5 Exception Handling
91
Overview
91
Types of Exception Handling and Priority
91
Exception Handling Operations
92
Exception Handling Vector Table
93
Resets
95
Types of Resets
95
Power-On Reset
95
Manual Reset
96
Address Errors
97
Address Error Sources
97
Address Error Exception Source
98
Interrupts
99
Interrupt Sources
99
Interrupt Priority
100
Interrupt Exception Handling
100
Exceptions Triggered by Instructions
101
Types of Exceptions Triggered by Instructions
101
Trap Instructions
101
Illegal Slot Instructions
102
General Illegal Instructions
102
Cases When Exceptions Are Accepted
103
Stack States after Exception Handling Ends
104
Usage Notes
106
Value of Stack Pointer (SP)
106
Value of Vector Base Register (VBR)
106
Address Errors Caused by Stacking for Address Error Exception Handling
106
Notes on Slot Illegal Instruction Exception Handling
107
Section 6 Interrupt Controller (INTC)
109
Features
109
Input/Output Pins
111
Register Descriptions
112
Interrupt Control Register 0 (ICR0)
113
IRQ Control Register (IRQCR)
114
IRQ Status Register (IRQSR)
116
Interrupt Priority Registers a to F and H to M (IPRA to IPRF and IPRH to IPRM)
119
Interrupt Sources
122
External Interrupts
122
On-Chip Peripheral Module Interrupts
123
User Break Interrupt
123
Interrupt Exception Handling Vector Table
124
Interrupt Operation
127
Interrupt Sequence
127
Stack after Interrupt Exception Handling
130
Interrupt Response Time
130
Usage Note
132
Section 7 User Break Controller (UBC)
133
Features
133
Register Descriptions
135
Break Address Register a (BARA)
136
Break Address Mask Register a (BAMRA)
136
Break Bus Cycle Register a (BBRA)
137
Break Data Register a (BDRA)
139
Break Data Mask Register a (BDMRA)
140
Break Address Register B (BARB)
141
Break Address Mask Register B (BAMRB)
142
Break Data Register B (BDRB)
143
Break Data Mask Register B (BDMRB)
144
Break Bus Cycle Register B (BBRB)
145
Break Control Register (BRCR)
147
Execution Times Break Register (BETR)
151
Branch Source Register (BRSR)
152
Branch Destination Register (BRDR)
153
Operation
154
Flow of the User Break Operation
154
Break on Instruction Fetch Cycle
155
Break on Data Access Cycle
155
Sequential Break
157
Value of Saved Program Counter
157
PC Trace
158
Usage Examples
159
Usage Notes
164
Section 8 Bus State Controller (BSC)
167
Features
167
Address Map
167
Access to On-Chip FLASH and On-Chip RAM
167
Access to On-Chip Peripheral I/O Register
168
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
171
Features
171
Input/Output Pins
177
Register Descriptions
178
Timer Control Register (TCR)
182
Timer Mode Register (TMDR)
186
Timer I/O Control Register (TIOR)
189
Timer Compare Match Clear Register (TCNTCMPCLR)
208
Timer Interrupt Enable Register (TIER)
209
Timer Status Register (TSR)
214
Timer Buffer Operation Transfer Mode Register (TBTM)
222
Timer Input Capture Control Register (TICCR)
223
Timer A/D Converter Start Request Control Register (TADCR)
225
Timer A/D Converter Start Request Cycle Set Registers
228
(TADCORA_4 and TADCORB_4)
228
Timer A/D Converter Start Request Cycle Set Buffer Registers
228
(TADCOBRA_4 and TADCOBRB_4)
228
Timer Counter (TCNT)
229
Timer General Register (TGR)
229
Timer Start Register (TSTR)
230
Timer Synchronous Register (TSYR)
232
Timer Counter Synchronous Start Register (TCSYSTR)
234
Timer Read/Write Enable Register (TRWER)
236
Timer Output Master Enable Register (TOER)
237
Timer Output Control Register 1 (TOCR1)
238
Timer Output Control Register 2 (TOCR2)
241
Timer Output Level Buffer Register (TOLBR)
244
Timer Gate Control Register (TGCR)
245
Timer Subcounter (TCNTS)
247
Timer Dead Time Data Register (TDDR)
248
Timer Cycle Data Register (TCDR)
248
Timer Cycle Buffer Register (TCBR)
249
Timer Interrupt Skipping Set Register (TITCR)
249
Timer Interrupt Skipping Counter (TITCNT)
251
Timer Buffer Transfer Set Register (TBTER)
252
Timer Dead Time Enable Register (TDER)
254
Timer Waveform Control Register (TWCR)
255
Bus Master Interface
256
Operation
257
Basic Functions
257
Synchronous Operation
263
Buffer Operation
265
Cascaded Operation
269
PWM Modes
274
Phase Counting Mode
279
Reset-Synchronized PWM Mode
286
Complementary PWM Mode
289
A/D Converter Start Request Delaying Function
328
External Pulse Width Measurement
332
Dead Time Compensation
333
TCNT Capture at Crest And/Or Trough in Complementary PWM Operation
335
Interrupt Sources
336
Interrupt Sources and Priorities
336
A/D Converter Activation
339
Operation Timing
341
Input/Output Timing
341
Interrupt Signal Timing
348
Usage Notes
352
Module Standby Mode Setting
352
Input Clock Restrictions
352
Caution on Period Setting
353
Contention between TCNT Write and Clear Operations
353
Contention between TCNT Write and Increment Operations
354
Contention between TGR Write and Compare Match
355
Contention between Buffer Register Write and Compare Match
356
Contention between Buffer Register Write and TCNT Clear
357
Contention between TGR Read and Input Capture
358
Contention between TGR Write and Input Capture
359
Contention between Buffer Register Write and Input Capture
360
TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection
360
Counter Value During Complementary PWM Mode Stop
362
Buffer Operation Setting in Complementary PWM Mode
362
Reset Sync PWM Mode Buffer Operation and Compare Match Flag
363
Overflow Flags in Reset Synchronous PWM Mode
364
Contention between Overflow/Underflow and Counter Clearing
365
Contention between TCNT Write and Overflow/Underflow
366
Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode
366
Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode
367
Interrupts in Module Standby Mode
367
Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection
367
MTU2 Output Pin Initialization
368
Operating Modes
368
Reset Start Operation
368
Operation in Case of Re-Setting Due to Error During Operation, Etc
369
Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc
370
Section 10 Port Output Enable (POE)
401
Features
401
Input/Output Pins
403
Register Descriptions
404
Input Level Control/Status Register 1 (ICSR1)
405
Output Level Control/Status Register 1 (OCSR1)
408
Input Level Control/Status Register 3 (ICSR3)
409
Software Port Output Enable Register (SPOER)
411
Port Output Enable Control Register 1 (POECR1)
413
Port Output Enable Control Register 2 (POECR2)
414
Operation
416
Input Level Detection Operation
416
Output-Level Compare Operation
418
Release from High-Impedance State
418
Interrupts
419
Usage Note
420
Pin State When a Power-On Reset Is Issued from the Watchdog Timer
420
Section 11 Watchdog Timer (WDT)
421
Features
421
Input/Output Pin for WDT
423
Register Descriptions
424
Watchdog Timer Counter (WTCNT)
424
Watchdog Timer Control/Status Register (WTCSR)
425
Notes on Register Access
427
Operation
428
Canceling Software Standbys
428
Using Watchdog Timer Mode
428
Using Interval Timer Mode
429
Usage Note
430
Section 12 Serial Communication Interface (SCI)
431
Features
431
Input/Output Pins
433
Register Descriptions
434
Receive Shift Register (SCRSR)
435
Receive Data Register (SCRDR)
435
Transmit Shift Register (SCTSR)
435
Transmit Data Register (SCTDR)
436
Serial Mode Register (SCSMR)
436
Serial Control Register (SCSCR)
439
Serial Status Register (SCSSR)
442
Serial Port Register (SCSPTR)
448
Serial Direction Control Register (SCSDCR)
450
Bit Rate Register (SCBRR)
451
Operation
462
Overview
462
Operation in Asynchronous Mode
464
Clock Synchronous Mode (Channel 1 in the SH7124 Is Not Available)
474
Multiprocessor Communication Function
483
Multiprocessor Serial Data Transmission
485
Multiprocessor Serial Data Reception
486
SCI Interrupt Sources
489
Serial Port Register (SCSPTR) and SCI Pins
490
Usage Notes
491
SCTDR Writing and TDRE Flag
491
Multiple Receive Error Occurrence
491
Break Detection and Processing
492
Sending a Break Signal
492
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
492
Note on Using External Clock in Clock Synchronous Mode
494
Module Standby Mode Setting
494
Section 13 A/D Converter (ADC)
495
Features
495
Input/Output Pins
497
Register Descriptions
498
A/D Data Registers 0 to 7 (ADDR0 to ADDR7)
499
A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1)
499
A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1)
502
A/D Trigger Select Register_0 (ADTSR_0)
504
Operation
508
Single Mode
508
Continuous Scan Mode
508
Single-Cycle Scan Mode
509
Input Sampling and A/D Conversion Time
509
A/D Converter Activation by MTU2
512
External Trigger Input Timing
512
2-Channel Scanning
513
Interrupt Sources
514
Definitions of A/D Conversion Accuracy
515
Usage Notes
518
Module Standby Mode Setting
518
Permissible Signal Source Impedance
518
Influences on Absolute Accuracy
518
Range of Analog Power Supply and Other Pin Settings
519
Notes on Board Design
519
Notes on Noise Countermeasures
520
Section 14 Compare Match Timer (CMT)
521
Features
521
Register Descriptions
522
Compare Match Timer Start Register (CMSTR)
523
Compare Match Timer Control/Status Register (CMCSR)
523
Compare Match Counter (CMCNT)
525
Compare Match Constant Register (CMCOR)
525
Operation
526
Interval Count Operation
526
CMCNT Count Timing
526
Interrupts
527
CMT Interrupt Sources
527
Timing of Setting Compare Match Flag
527
Timing of Clearing Compare Match Flag
527
Usage Notes
528
Module Standby Mode Setting
528
Conflict between Write and Compare-Match Processes of CMCNT
528
Conflict between Word-Write and Count-Up Processes of CMCNT
529
Conflict between Byte-Write and Count-Up Processes of CMCNT
530
Compare Match between CMCNT and CMCOR
530
Section 15 Pin Function Controller (PFC)
531
Register Descriptions
539
Port a I/O Register L (PAIORL)
540
Port a Control Registers L1 to L4 (PACRL1 to PACRL4)
540
Port B I/O Registers L and H (PBIORL and PBIORH)
551
Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1)
552
Port E I/O Register L (PEIORL)
557
Port E Control Registers L1 to L4 (PECRL1 to PECRL4)
557
IRQOUT Function Control Register
567
Usage Notes
568
Section 16 I/O Ports
569
Port a
570
Register Descriptions
571
Port a Data Register L (PADRL)
571
Port a Port Register L (PAPRL)
575
Port B
577
Register Descriptions
577
Port B Data Registers H and L (PBDRH and PBDRL)
578
Port B Port Registers H and L (PBPRH and PBPRL)
581
Port E
584
Register Descriptions
586
Port E Data Register L (PEDRL)
586
Port E Port Register L (PEPRL)
589
Port F
591
Register Descriptions
591
Port F Data Register L (PFDRL)
592
Section 17 Flash Memory
593
Features
593
Overview
595
Block Diagram
595
Operating Mode
596
Mode Comparison
597
Flash Memory Configuration
598
Block Division
598
Programming/Erasing Interface
599
Input/Output Pins
601
Register Descriptions
601
Registers
601
Programming/Erasing Interface Registers
604
Programming/Erasing Interface Parameters
610
On-Board Programming Mode
625
Boot Mode
625
User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version)
629
Protection
638
Hardware Protection
638
Software Protection
639
Error Protection
639
Usage Notes
641
Interrupts During Programming/Erasing
641
Other Notes
643
Supplementary Information
645
Specifications of the Standard Serial Communications Interface in Boot Mode
645
Areas for Storage of the Procedural Program and Data for Programming
672
Off-Board Programming Mode
676
Section 18 RAM
677
Usage Notes
678
Module Standby Mode Setting
678
Address Error
678
Initial Values in RAM
678
Section 19 Power-Down Modes
679
Features
679
Types of Power-Down Modes
679
Input/Output Pins
681
Register Descriptions
681
Standby Control Register 1 (STBCR1)
682
Standby Control Register 2 (STBCR2)
683
Standby Control Register 3 (STBCR3)
684
Standby Control Register 4 (STBCR4)
685
Standby Control Register 5 (STBCR5)
686
Standby Control Register 6 (STBCR6)
687
RAM Control Register (RAMCR)
688
Sleep Mode
689
Transition to Sleep Mode
689
Canceling Sleep Mode
689
Software Standby Mode
690
Transition to Software Standby Mode
690
Canceling Software Standby Mode
691
Module Standby Mode
692
Transition to Module Standby Mode
692
Canceling Module Standby Function
692
Usage Note
692
Current Consumption While Waiting for Oscillation to be Stabilized
692
Executing the SLEEP Instruction
692
Section 20 List of Registers
693
Register Address Table (in the Order from Lower Addresses)
694
Register Bit List
702
Register States in each Operating Mode
716
Section 21 Electrical Characteristics
725
Absolute Maximum Ratings
725
DC Characteristics
726
AC Characteristics
729
Clock Timing
730
Control Signal Timing
732
Multi Function Timer Pulse Unit 2 (MTU2) Timing
735
I/O Port Timing
737
Watchdog Timer (WDT) Timing
738
Serial Communication Interface (SCI) Timing
739
Port Output Enable (POE) Timing
741
A/D Converter Timing
742
Conditions for Testing AC Characteristics
743
A/D Converter Characteristics
744
Flash Memory Characteristics
745
Usage Note
746
Notes on Connecting V
746
Capacitor
746
Appendix
747
Pin States
747
Product Code Lineup
751
Package Dimensions
752
Main Revisions and Additions in this Edition
757
Index
773

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