Xilinx Virtex-5 FPGA ML555 User Manual page 26

Chapter 3: Hardware Description
add-in card. More than one PRSNT2_B pin is defined in the x4, x8, and x16 PCI Express
connectors; these are necessary to support up-plugging of the add-in card. Up-plugging is
defined as plugging a smaller link card into a larger link connector. The ML555 board can
be plugged into x8 or x16 lane link connectors.
Prior to installation in the PCI Express system unit, connector P45 must be configured to
indicate the number of PCI Express lanes used in the design, as shown in
Table 3-2: Presence Detect Configuration Header for PCI Express Designs (P45)
Notes:
1. P45 pins 2, 4, and 6 are all connected to PCIE_PRSNT1_B on connector P13 pin A1.
2. See
Downshifting is defined as plugging an add-in card into a connector that is not fully routed
for all of the lanes. In general, downshifting is not allowed and is physically prevented. An
exception is the x8 connector, in which the system designer can choose to route only the
first four lanes; a x8 lane card must function as a x4 lane card in this scenario. The ML555
board can be used as either a x4 or a x8 lane card depending upon the user design loaded
into the FPGA.
For development purposes, several companies offer x16 to x1 adapters that permit
plugging multilane add-in cards into single lane PCI Express system unit connectors. The
adapter is not provided with the ML555 development kit.
Table 3-3
pins, and GTP_DUAL tile location assignments.
26
Number of
Active Lanes in Shunt Position on Connector P45
Design
1 Install shunt on connector P45 pins 5 - 6
4 Install shunt on connector P45 pins 3 - 4
8 Install shunt on connector P45 pins 1 - 2
Figure 3-3, page 23 for the location of configuration header P45.
shows the correlation between PCI Express signals, P13 add-in card pin, FPGA
www.xilinx.com
Table
Physical Connection at
Connector P13
(1)
PRSNT1_B PRSNT2_B
P13-A1
P13-A1
P13-A1
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R
3-2.
P13-B17
P13-B31
P13-B48