Intel NetStructure ZT 5515 Product Specification page 79

Table 38. Watchdog (79h)
®
Intel NetStructure
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Bit
Stage 2 Monitor (Reset Monitor)
Monitors the second stage (Reset) timer status.
Read Value:
0 = Watchdog has not timed out since power up or since this bit was last set to 0.
1 = Watchdog reset timeout occurred since power up or since bit was last set to
0.
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Write Value:
0 = Sets this bit to 0.
1 = No effect.
Power Up Value = 0.
A hard reset not caused by a watchdog timeout will set this bit to 0.
Stage 1 Monitor (NMI or INIT Monitor)
Monitors the first stage (NMI or INIT) timer status.
Read Value:
0 = Watchdog has not timed out since power up or since this bit was last set to 0;
1 = Watchdog timed out and either:
• NMI output was asserted if bit 3 = 0; or
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• INIT output was asserted if bit 3 = 1.
Write Value:
0 = Sets this bit to 0.
1 = No effect.
Power Up Value = 0.
A hard reset will set this bit to 0.
NMI or INIT
Selects between generating an NMI or a CPU INIT.
Read Value:
0 = NMI
1 = INIT
3 This bit is set to 0 at reset.
Write Value:
0 = NMI is generated when the watchdog times out.
1 = INIT is generated when the watchdog times out.
Power Up Value = 0.
A hard reset will set this bit to 0.
Terminal Count (TermCnt2...TermCnt0)
Read Value: Reflects the value written to bits 2 through 0.
Write Value: These bits determine the terminal count of the watchdog.
Below is the minimum timeout period. The watchdog times out in no less than
the minimum value. The nominal timeout period is 30% longer than the
minimum.
2:0
000 = 250 ms 100 = 32 s
001 = 500 ms 101 = 64 s
010 = 1 s 110 = 128 s
011 = 8 s 111 = 256 s
Power Up Value = 000.
A hard reset will set these bits to 000.
TM
ZT 5515 Compute Processor Board Technical Product Specification
Description
System Registers
79