Cpu Configuration - IEI Technology DRPC-120-BTi User Manual

DRPC-120-BTi Embedded System

Odd

Mark

Space

Stop Bits [1]
Use the Stop Bits option to specify the number of stop bits used to indicate the end of a
serial data packet. Communication with slow devices may require more than 1 stop bit.

1

2

5.3.6 CPU Configuration

Use the CPU Configuration BIOS menu (BIOS Menu 10) to view detailed CPU
specifications and configure the CPU.
The parity bit is 0 if the number of ones in the data
bits is odd.
The parity bit is always 1. This option does not
provide error detection.
The parity bit is always 0. This option does not
provide error detection.
Sets the number of stop bits at 1.
D
EFAULT
Sets the number of stop bits at 2.
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