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cPCI-MXS64 Technical Reference Manual
3.2.4 21154 PCI-to-PCI Bridge
The 21154 is configure as a 32/64-bit 33MHz PCI-to-PCI bridge that allows the board to
support up to seven cPCI slot on its secondary PCI bus through a passive backplane. The
bridge is fully compliant with the PCI Local Bus Specification, Rev. 2.1. It provides full
support for delayed transactions, which enables the buffering of memory read, I/O and
configuration transactions. The 21154 have separate posted write, read data and delayed
transaction queues with a high buffering capability.
In addition, it supports buffering of simultaneous multiple posted writes and delayed
transactions in both directions.
The PCI-to-PCI bridge allows the Primary and Secondary PCI buses to operate
concurrently. This means that a master and a target on the same PCI bus can communicate
while the other PCI bus is busy. This traffic isolation may increase system performance in
applications where system resources are highly used.
3.2.5 82371AB PCI-to-ISA Bridge / IDE Xcelerator (PIIX4)
The PCI-to-ISA bridge is configured to support signals to directly drive IDE interfaces,
USB ports, extra communication ports (Serial Ports 3 and 4), and standard Serial Ports (1
and 2), floppy disk drives, mouse and keyboard through a super I/O controller
(FDC37C672).
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