Display Of Bus Information On The M32C Debugger - Renesas Emulator Debugger M16C PC4701 User Manual

7.11.6 Display of bus information on the M32C Debugger

From left to right, the contents are as follows:
• Address
• The status of the address bus
• Data
The status of the data bus
•
BUS
The width of the external data bus ("8b" for an 8-bit data bus, and "16b" for a 16-bit data bus)
• BIU
This shows the status between the BIU (bus interface unit) and memory, and BIU and I/O.
Representation
-
WAIT
RBML
F
QC
RWML
INT
RB
WB
DRB
DW B
RW
WW
DRW
DWW
• R/W
Shows the status of the data bus ("R" for r ead, "W" for wr it e, "-" for no access).
• RWT
This signal shows the effective position in the bus cycle ("0" when effective. Address, Data, and
BIU signals are valid when RWT is "0".
• CPU, OPC, OPR
This shows the signal between CPU and BIU. In the column "CPU", the data shows whether CPU
accesses BIU or not . In the Column "OPC", the data shows the byte size of read operat ion code.
In the Column "OPR", the data shows the byte size of read operand.
BIU statu s
No access
Executing wait instruction
Read access (b ytes, ML on)
Fetch access
Discontinuous Fetch access
Read access (words, ML on)
Interrupt acknowledge
Read access (bytes)
Write access (bytes)
Read access by DMA (bytes)
Write access by DMA (bytes)
Read access (words)
Write access (words)
Read access by DMA (words)
Write access by DMA (words)
176
(q ueue buffer)