Timing Requirements - Renesas Emulation Pod M306N4T3-RPD-E User Manual

(3) Timing Requirements

Table 5.4 and Figure 5.3 show the timing requirements.
Table 5.4 Timing requirements
Symbol
tsu(DB-RD) Data input setup time
tsu(RDY-BCLK) RDY* input setup time
tsu(HOLD-BCLK) HOLD* input setup time
th(RD-DB) Data input hold time
th(BCLK-RDY)
RDY* input hold time
th(BCLK-HOLD) HOLD* input hold time
td(BCLK-HLDA) HLDA* output delay time
Common to "with wait" and "no-wait" (actual MCU)
Common to "with wait" and "no-wait" (this product)
Figure 5.3 Timing requirements
* Compared with the actual MCU, this product enters high-impedance state after a 0.5 cycle delay.
Item
( 59 / 76 )
Vcc1 = Vcc2 = 5 V
Actual MCU
This product
[ns]
[ns]
Min. Max. Min.
40 55
30 45
40 55
0
See left
0
See left
0
See left
40
See left
Max.