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(4) Timing Requirements
Table 5.5, Figures 5.4 and 5.5 show timing requirements in the memory expansion and microprocessor
modes.
Table 5.5 Timing requirements (V
Symbol
Tsu (DB-RD)
Data input setup time
Tsu (RDY-BCLK)
RDY* input setup time
Tsu (HOLD-BCLK)
HOLD* input setup time
Th (RD-DB)
Data input hold time
Th (BCLK-RDY)
RDY* input hold time
Th (BCLK-HOLD)
HOLD* input hold time
Td (BCLK-HLDA)
HLDA* output delay time
*1 Minimum 7 ns (The definition is different from that of actual MCUs. For details, see Figure 5.5.)
Memory expansion and microprocessor modes
(only for "with wait")
BCLK
RD
(separate bus)
WR, WRL, WRH
(separate bus)
RD
(multiplex bus)
WR, WRL, WRH
(multiplex bus)
RDY input
Figure 5.4 Timing requirements
= 5 V)
CC
Item
Conditions:
• V
= 5 V
CC
• Input timing voltage: V
• Output timing voltage: V
( 59 / 76 )
Actual MCU
This product
[ns]
[ns]
Min.
Max.
Min.
Max.
40
See left
30
45
40
*1
0
See left
0
See left
0
See left
40
See left
= 1.0 V, V
= 4.0 V
IL
IH
= 2.5 V, V
= 2.5 V
OL
OH
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