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7.4 Timing Requirements
Table 7.4 and Figure 7.4 show timing requirements when using the memory expansion mode and
microprocessor mode.
Table 7.4 Timing requirements (Vcc = 5 V)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
th(BCLK-HLDA)
Note 1. tsu(HOLD-BCLK) =
Symbol
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
Parameter
9
10
x3
+ 20
f(BCLK)x2
( 37 / 48 )
M306V0EEFP
M306V0T-RPD-E
[ns]
Min.
Max.
Min.
40
-
80
30
-
50
40
-
(Note 1)
0
-
0
0
-
0
0
-
0
-
40
-
[ns]
Max.
-
-
-
-
-
-
40
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