Test The Next Channels; To Testthe Single-Clock, Single-Edge, State Acquisition (Logic Analyzer) - HP 1660E Series Service Manual

Testing Performance
To testthe single-clock, single-edge, state acquisition (logic analyzer)
~(format
t1ACHnJE I )
~ ~
510le AcqUlslllon MOde
I~ ~
FilII ChonnelJ1V
Iwmor~/IOOMHz ~ ~ J
Moster CloCI
DUALS'
O\~
802(J!!J
03~ 804~
L ( Setup/Hold
I
•
11 Press the blue shift key, then press the Run key. If two to four acquisitions are
obtained without the "Stop Condition Satisfied" message appearing, then the test
passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the
performance test record.
12 Test the next clock.
a Press the Format key, then select Master Clock.
b Turn off and disconnect the clock
just
tested.
c Repeat steps
11,
12, and 13 for the next clock edge listed in the table in step 10, until
all listed clock edges have been tested.
13 Test the next setup/hold combination.
a in the logic analyzer Format menu, press Master Clock.
b Turn off and disconnect the clock
just
tested.
c Repeat steps 1 through 14 for the next setuplhold combination listed in step 1 on
page 3-30, until all listed setuplhold combinations have been tested.
When aligning the data and clock waveforms using the oscilloscope,
align
the waveforms
according to the setup time of the setuplhold combination being tested, +0.0 ps or -100 ps.
Test the next channels
Connect the next combination of data channels and clock channels, then test them.
Start on page 3-27, "Connect the logic analyzer," connect the next combination, then continue
through the complete test.
3-36