HP 1660E Series Service Manual page 65

Logic analyzers
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Testing Performance
To test the multiple-clock. multiple-edge. state acquisition (logic analyzer)
2 Set up the Format menu.
a Press the Format key. Select State Acquisition Mode, then select
Full
Channel/4K
Memory/lOOMHz.
b Select the field to the right of each Pod field, then select ECL. The screen does not
show all Pod fields at one time. Use the knob to access more Pod fields.
..
ldbel~
..
15
LObI
81,
Lob1
LOb;;
LOb.l
LObS
LObo
LOb?
LOba
67 .
15
·11 ..
I
Pod A2
Eel
)
t1o~ter
Clocl
15
. 67
II
I
3 Set up the Trigger menu.
a Press the Trigger key. Select Modify Trigger, then select Clear Trigger, then select All.
b Select the Count Off field, then select Time in the pop-up menu. Select Done to exit
the menu.
c Select the field labeled 1 under the State Sequence Levels. Select the field labeled
"anystate", then select "no state." Select Done to exit the State Sequence Levels menu.
d Select the field next to the pattern recognizer "a," under the label Labl. Type the
following for your logic analyzer, then press Select.
HP 1660E/ESIEP - "OOAA"
HP 1662E1ESlEP - "OOAA"
HP 1661E/ESIEP - "OO2A"
HP 1663E1ESlEP - "OOOA"
(
Anol~zer
](
TrIgger
tlACHINE 1
)
S (0
to sequence
Leye I s
~
While storlng
~no
stote"
~
TRIGGER on "0"
1 lime
t~
St';>re "MUSIOlO"
o
Arming
(antral
ACqU1Sl
tlon
Control
Count
Time
3-39

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