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Testing Performance
To
testthe single-clock, multiple-edge, state acquisition (logic analyzer)
d Adjust the pulse generator channel 2 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
,
il
OAT A SIGNAL
+
i
-'+~~~i1
I
--J
I
-1~1
...
+...
l
- -
1---SeIUP Tlrne---
I
CLOCK SIGNAL
I
,
I
I
I
-H--H
II
,
I-H-t -
1
+t-H~
I
1
'
1
t
16SSS
l
tJ1Z
3 Select the clock to be tested.
a Select the clock field to be tested, then select the clock as indicated in the table. The
first time through this test, use the top multiple-edge clock in the following table.
Clocks
J!
Kt
Lt
Mt
Nt
Pt
b Connect the clock to be tested to the pulse generator channell output.
c Select Done to exit the Master Clock menu.
( AJlOly:er)(
Filrffiot
!1"CHItlE I
)
~ ~
St"'to
AcqUl~ltlOJl
Node
I~
(5ym~OlS)
FUll Chonnd/.l!' MemoryIlOOt1K= ~
rlilstor Clocl:
L
(
SHUl'lIlald
EJ
3-57
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