HP 1660E Series Service Manual page 61

,
,
Testing Performance
To
testthe single-clock, single-edge, state acquisition (logic analyzer)
9 Using the Delay mode of the pulse generator channell, position the pulses
according to the setup/hold combination selected, +0.0 ps or -100 ps.
a On the Oscilloscope, select [Define meas] Define
t;.
Time - Stop edge: falling.
b On the oscilloscope, select [Shift] - width: channel 2, then select [Enter] to verify the
clock signal pulse width (- width(2)). If the pulse width is outside the limits, adjust the
pulse generator channell width until the clock pulse width is 3.500 ns, +0 ps or -100
ps.
c On the oscilloscope, select [Shift]
t;.
Time. Select Start src: channell, then select
[Enter] to display the setup time
(t;.
Time(1)-(2)).
d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setuplhold combination selected,
+0.0
ps or
-100
ps.
DATA
SIGNA~
f
I
==FF~H
I
f
-
, ,
+~
Tlme-L --Se1up
11
(LOCK SiGNAl
-.-j-+-I-+-+-+-+-~~I--H-.-j-H-H.-j-+--+-t~-.-j-+-
-f+.H-H+~-H-j'-H-~
1 .
I
1
16':65WOS
10 Select the clock to be tested.
a In the Master Clock menu, select the clock field to be tested, then select the clock
edge as indicated in the table. The first time through this test, use the top clock and
edge.
Clocks
J.l-
K.l-
L.l-
M.l-
N.l-
P.l-
b Connect the clock to be tested to the pulse generator channell output.
c Select Done to exit the Master Clock menu (see illustration next page).
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