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Testing Performance
To testthe multiple-clock, multiple-edge, state acquisition (logic analyzer)
10 Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained
without the "Stop Condition Satisfied" message appearing, then the test passes.
Press Stop to halt the acquisition. Record the Pass or Fail results in the
performance test record.
11 Test the next clocks.
a In the logic analyzer Format menu, select Master Clock.
b
Tum
off and disconnect the clocks
just
tested.
c Repeat steps 2 through 12 for the next clock edges listed
in
the table in step 4, until
all
listed clock edges have been tested.
12 Test the next setuplhold combination.
a
In
the logic analyzer Format menu, select Master Clock.
b
Tum
off and disconnect the clocks
just
tested.
c Repeat steps 1 through 12 for the next setuplhold combination listed in step 1 on
page 342, until
all
listed setup/hold combinations have been tested.
When
aligning
the data and clock waveforms using the oscilloscope, align the waveforms
according to the setup time of the setup/hold combination being tested, +0.0 ps or -100 ps.
Test the next charmels
Connect the next combination of data channels and clock channels, then test them.
Start on page 3-40 "Connect the logic analyzer," connect the next combination, then continue
through the complete test.
3-48
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