HP 1660E Series Service Manual page 69

Logic analyzers
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Testing Performance
To test the multiple-clock. multiple-edge. state acquisition (logic analyzer)
0r TA SiGNAL
f
I
I
I
i
I
I
T
1~~I+'jrH+r:'-'-T'~'~""H-H+H~~+
,
I
16555WO-
3 Check the data pulse width. Using the oscilloscope verify that the data pulse width
is
4.500 ns, +0
ps or
-100 PSI
a In the oscilloscope Timebase menu, select Scale: 1.000 ns/div.
b In the oscilloscope Timebase menu, select Position. Using the oscilloscope !mob,
position the data waveform so that the waveform
is
centered on the screen.
c On the oscilloscope, select [Shift]
+
width: channell, then select [Enter] to display the
data signal pulse width
(+
width (I)).
d
If
the pulse width is outside the limits, adjust the pulse generator channel 2 width until
the pulse width
is
within limits.
"
r
OAf A SIGNAL
I
_H~~+[+H+:::
++-H I
,
"fH+H+'+I-H+~
:se Width
I
CLOCK SIGNAL
I
I
-+-t-t-t-+-t--H-t--I-t~-j-+++-t-t-t
t-+-
f-t-t-H-t-l-I-H
I
I
j
I
!
-
I
I
165SSW08
3-43

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