Characteristics (Pattern Generator) - HP 1660E Series Service Manual

General Information
Characteristics (pattern generator)
Characteristics (pattern generator)
The HP 1660EP logic analyzers also include the following characteristics:
Output channels
Memory depth
Logic levels (data pods)
Data inputs
Clock outputs
Clock input
Internal clock period
External clock period (user supplied)
External clock duty cycle
Maximum number of "IF condition"
blocks at 50 MHz clock
Maximum number of different macros
Maximum number of lines in a macro
Maximum number of macro invocations
Maximum number of Repeat loop
invocations
Maximum number of Wait event patterns
1-6
16 channels at 200 MHz clock; 32 channels at
100 MHz clock
258,048 vectors
TTL, 3-state TTlJ3.3v, 3-state
TTUCMOS,
ECL terminated, ECL unterminated, and differential
ECL (without pod)
3-bit pattern - level sensing (clock pod)
Synchronized to output data, delay of 11 ns in 9 steps
(clock pod)
DC to 200 MHz (clock pod)
Progranunable from 5 ns to 250 Ils in a 1, 2, 2.5, 4, 5, 8
sequence
DC to 200 MHz
2 ns minimum high time
1
100
1024
1,000
1,000
4