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Testing Performance
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)
Connect the logic analyzer
1 Using the 6-by-2 test connectors, connect the first combination of logic analyzer
clock and data channels listed
in
one of the following tables to the pulse generator.
If
you are testing an HP l660ElES/EP or HP l66lE/ESIEP, you
will
repeat this test for the
second combination.
2 Using SMA cables, connect channell, channel 2, and trigger of the oscilloscope to
the pulse generator.
Connect the HP 1660EjES/EP or HP 1661 EjES/EP Logic Analyzer to the Pulse Generator
Testing
Combinations
2
Connect to
HP8t33A
Channel 2 OUlput
Pod 1, channel 3
Pod 3, channel 3
Pod 5, channel 3
Pod 7, channel 3
Pod 1, channel 11
Pod 3, channel 11
Pod 5, channel 11
Pod 7, channel 11
Connect to
HP 8t33A Channel 2
Output
Pod 2, channel 3
Pod 4, channel 3
Pod 6, channel 3
Pod 8, channel 3
Pod 2, channel 11
Pod 4, channel 11
Pod 6, channel 11
Pod 8, channel 11
Connect to
HP 8t33A Channelt
OUlput
J-clock
M-clock
N-clock
J-clock
M-clock
N-clock
11:1
3-40
813] Opll'" 00)
~'1rl
--,
""'••' ,.,..,0,',.., """.,
(0)
(~
0
Co)
Pads 1,3,5.7
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