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Testing Performance
To
test
the single-clock, single-edge,
state
acquisition (logic analyzer)
2 Disable the pulse generator channell COMP (with the LED off).
3 Using the Delay mode of the pulse generator channell, position the pulses
according to the setup time of the setup/hold combination selected,
+0.0
ps or
-100
ps.
a On the Oscilloscope, select [Defme meas] Define
l>.
Time - Stop edge: rising.
b In the oscilloscope ttmebase menu, select Position. Using the oscilloscope !mob,
position the rising edge of the clock waveform so that it is centered on the display.
c On the oscilloscope, select [Shift]
l>.
TIme, then select [Enter] to display the setup time
(l>.
Ttme(I)-(2)).
d Adjust the pulse generator channell Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
,
11
OA TA SIGNA4-
f:
,
~
,II", ,
!
I I I
I
I
~
,
L
,--Selup Time
~-,
~
(LOCK SIGNAL
,
,
,
,
f
H~t::
,
,
--+--+--l-+-+-H-++-J~
~~~
,
I
I
I
,
,
,
.
,
,
16555WQ
3-32
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