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Testing Performance
To testthe single-clock, multiple-edge, state acquisition (logic analyzer)
2 Set up the Format menu.
a Press the Fonnat key. Select State Acquisition Mode, then select
Full
ChanneV4K
Mernory/l00MHz.
b Select the field to the right of each pod field, then select ECL. The screen does not
show all pod fields at one time. Use the knob to access pod fields not shown on the
screen.
~(
Format
M';CHItlE I
)
S\lJt~ AcquisItIon M(ld~
[Noster Clocl
tU II (honn" l/olf; Memor'J/](oOMH: "';':::;:;:::::;:::;:
~
Eel I
Pod A3
_-cr:>-_
Moster CIOCI
15.
87
,. 0
Labl
Ell
Lob2
LOll3
Lob-l
LaoS
Lobo
LOll7
Lobll
..... I
L e i
,,-,,-,,-,,-,,-,,-,-,I
L e i
,,-,,-,,-,,-,,-·CC··
col
HP
1662E1ESlEP - "OOAA"
HP
1663E1ESIEP - "OOOA"
3 Set up the Trigger menu.
a Press the Trigger key. Select Modify Trigger, select Clear Trigger, then select All
in
the pop-up menu.
b Select Count Off. Press Select again, then select Time
in
the pop-up menu. Select
Done to exit the menu.
c Select the field labeled 1 under the State Sequence Levels. Select the field labeled
"anystate," then select uno state.1! Select Done to exit the State Sequence Levels menu.
d Select the field next to "a," under the label Lab 1. Type the following for your logic
analyzer, then press the Select key.
HP 1660E/ESIEP - "OOAA"
HP 1661E/ESIEP - "OO2A"
( Ana I ",W )(
t1ACHWE:
,
)
~
~
Trlgger
Slote Sequenc(t Level"
TImer
ArmIng
I
'
,
Q
Hlllle slorlrlg "no stolt>"
..
Control
TP.1GGER on "0"
,
\ 1m"
ACqUISltlonl
. .
Control
0
Store "onystOll'''
[
Count
I
TIme
MOOI
fy
J
Tr 19ger
~.;el+
~
"T~~ ~
,
.-
"
)~
,
~
"
~
3-51
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