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Until : Indefinite
1.6.3.2 Initialize sequence
Flow Chart of initialize sequence
■
Procedure of initialization sequence is described below. Refer to "Register specifications" for the initialization
commands and set contents.
Proced
Set contents
ure
1
Power-on
2
Cancel power save
3
Setting Up and Down converter
circuit
4
Cancel power save of column circuit
5
Set the multiple value of PLL and
the clock division supplied to PLL
6
Another PLLREG setting
7
Wait for stabilizing the oscillation of
PLL
8
Cancel the reset of internal clock
division.
9
Cancel the reset of Up and Down
converter circuit.
10
Wait for stabilizing the output
voltage of Up and Down converter
circuit.
11
Setting registers except PLLREG.
12
Cancel TG reset
13
Input HD
14
Start the imaging.
2015/10/01
Enactment
Revision
Specifications
Table 1.6.7 List of initialize Sequence
Refer to 1.6.3.1 for Power-On Sequence.
1usec or more after set ting PSV pin to "High" 10T or more after
Power-on to cancel the power save and hardware reset, please
supply clock to the MCLK pin. Then it becomes allowable to access
the register PLLREG by the 3-wire serial I/F.
Use the 3-wire serial I/F for setting the Up and Down converter circuit
to internal.
Set the register by the 3-wire serial I/F.
Set the register by the 3-wire serial I/F.
Set the register by the 3-wire serial I/F.
Wait until PLL output clock is stabilized.
The register other than PLLREG can not be written normally when
the waiting time for PLL oscillation stability is not enough.
Set the register by the 3-wire serial I/F.
The clock can be supplied to the internal logic by canceling the reset
of the internal clock division circuit
And it becomes allowable to access the registers other than
PLLREG by the 3-wire serial I/F.
Set the register by the 3-wire serial I/F.
If the waiting time is missing, normal image would not be achieved.
Set the register by the 3-wire serial I/F.
It can access to the TG setting register in parallel with procedure11
Set the register by the 3-wire serial I/F.
Cancel the reset setting of internal counter circuit in TG.
It is recommended to input more than 5 times HD.
If it is not possible to input more than 5 times HD, exposure time may
be limited in 1st output frame.
For more information about this limitation, please refer to
"[Note] When 5 times or more HD can not be input after canceling
TG reset." in this chapter.
Generalplus Technology Inc.
MN34120PAJ
Total Page
96
Description
Panasonic Semiconductor Solutions Co., Ltd.
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