Panasonic MN34120PAJ Manual page 57

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Data output timing (V-cycle)
■
After period of Front-Blanking (V_FRONT) from VD and HD, the record pixel (V_PIX) is sequentially output.
Afterwards, it is period of Back-Blanking (V_BACK).Each Blanking period and record pixel depends on driving
mode. Please refer to the output timing table (Table 1.7.5) in details. Moreover, when you use the LVDS
power save function, the power save cancel timing and the power save shift timing can be set by the unit of
Hcycle. Please refer to the MN34120PA register specifications in details.
VD
HD
LVDS
Blanking
(Power save Off)
LVDS Hi-z
(Power save On)
T
pulvds
V_FRONT
Table 1.7.6 LVDS enable / disable Time (Reference design)
LVDS enable time
LVDS disable time
※ α is an internal system delay time (380 ns).
2015/10/01
Enactment Revision
Specifications
HCYCLE
0Line BLK
LVDS Power save cancel timing
Blanking 0Line BLK
Figure 1.7.2.1-2 Data output timing chart (V-cycle)
Symbol
Tpulvds
Tpdlvds
VCYCLE
1Line BLK 2Line
LVDS Power save shift timing
1Line BLK 2Line
V_PIX
Min. Typ.
1.5+α
0.1+α
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
Total Page
Page
96
BLK (n-1)Line Blanking
Hi-z
BLK (n-1)Line Blanking
T
pdlvds
V_BACK
Max. Unit
 
 
55
μs
μs