Send (Write) Timing For Register - Panasonic MN34120PAJ Manual

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1.6.1.1 Send (Write) Timing for Register

The timing of " transmission to PLLREG register (Write) " and " transmission to "registers other than the
PLLREG register" (Write) " is different. Please refer to the following content in details.
■ PLLREG register
PLLREG is a register that sets PLL setting and the circuit of dividing frequency setting. The range in the
register address is as follows.
0x0000  0x0011
PSV
SCS
SCK
SI A0
tRST_p tSCS0
Figure 1.6.1.1-1 Definition of Send (Write) Timing for PLLREG Register
Table 1.6.2 AC Characteristics of Send (Write) Timing for PLLREG Register (Reference design)
Parameter Min.
tRST_p 30
tSCS0 30
tSCS1 30
tSCS2 60
tSCW 28.57
tSST 5
tSHD 5
2015/10/01
Enactment Revision
Specifications
A1 A2 A13 A14 Low
tSCW tSST tSHD
Typ. Max. Unit
- - ns
- - ns
- - ns
- - ns
- 10000 ns
- - ns
- - ns
D0 D1 D7 D8 D9
Remarks
From the reset release (PSV=High) to "SCS = Low".
From "SCS=Low" to the "SCK input".
From the "last-SCK input" to the "SCS rising edge".
-
SCK cycle (100 kHz ~35 MHz)
Serial I/F SETUP-time for SCK
Serial I/F HOLD-time for SCK
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
Total Page
Page
31
96
D14 D15
tSCS1 tSCS2