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Until : Indefinite
HD/VD timing specifications
■
VD
HD
*Active edge of VD and HD can be changed by the register setting.
Figure 1.2.2.1-3 Definition of HD/VD input timing specifications
Table 1.2.3 AC characteristics of HD/VD input signal (Reference design)
Symbol
Thdly
MCLK timing specifications
■
MCLK
Figure 1.2.2.1-4 Definition of MCLK input timing specifications
Table 1.2.4 AC characteristics of MCLK input signal (Reference design)
Parameter
Clock duty ratio
2015/10/01
Enactment
Revision
Specifications
Thdly
(Figure is described by the rising edge standard.)
Min.
Typ.
-5 ns
-
50%
T
H
Symbol
Min.
T
/T
45
H
L
50%
50%
Max.
HCYCLE－10T
T
L
Typ.
Max.
Unit
50
55
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
Total Page
Page
14
96
Unit
MCLK
Remarks
%
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