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Panasonic MN34120PAJ Manual

Panasonic MN34120PAJ Manual

Area sensor
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Number
96
－
Product Standards
Area Sensor
MN34120PAJ
Ver 1.02
Panasonic Semiconductor Solutions Co., Ltd.
Established by
Applied by
Checked by
Prepared by
2015/10/01
Generalplus Technology Inc.
Enactment
Revision
Panasonic Semiconductor Solutions Co., Ltd.

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Summary of Contents for Panasonic MN34120PAJ

  • Page 1 Total Page Page Number － Product Standards Area Sensor MN34120PAJ Ver 1.02 Panasonic Semiconductor Solutions Co., Ltd. Established by Applied by Checked by Prepared by 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 2 About This Manual Organization ■ In this LSI manual, the outline, functions, and operation of MOS-type image sensor are described for the purpose of providing necessary information about the use of this type of image sensor to users. Manual Configuration ■...

  • Page 3: Table Of Contents

    1.7.4.1 LVDS Output Format (Recognition Code) ..........62 1.7.4.2 LVDS 1ch 8port / 2ch 4port Format Output .......... 63 1.7.4.3 LVDS 1ch 6port / 2ch 3port Format Output .......... 66 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 4 1.9 Packing Specification ..................89 1.10 Notes on Device Handling ................91 1.10.1 Notes on Device Handling and Storage ........... 91 1.10.2 Guarantee for MOS type Image Sensor ........... 96 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 5: Chapter1 Specifications

    MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Chapter1 Specifications 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 6: Product Summary

    Full scan mode(no mixing, no skipping) High speed mode , Monitor mode (Live view) HD movie mode (1080p / 720p) 1080/60p（V2/2mix_c H2mix Mode) 720/60p（V2/3mix_c H3mix Mode) Full scan mode to free vertical cutout 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 7 Parallel column AD converter, signal processing part and functional circuits of various kinds. Serial Power External supply Pixel Area 　 1.2V 　 1.8V MCLK 　 3.3V Output IF LVDS Parallel A/D converter of row Figure 1.1.1 Block Diagram 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 8 Gr R Gr R Gr R Gr R Gr R Gr R ・ R Gr R Gr R Gr R Gr R Gr R ・ ・ ・ effective pixel area(include trans ient) Figure 1.1.2 Pixel Array Configuration 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 9 SDOD5P LVDS outpu (1ch mode: clock +) Digital GND AGNDP Analog GND AGNDP Analog GND AGNDR Analog GND SDOD6M LVDS output (port13 data -) Zdiff=100Ω(under ±1%) SDOD6P LVDS output (port13 data +) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 10 ・The decoupling capacitor must be used the temperature property B rank more over. ※1 ~ ※2 There is a possibility that the change of the recommended value is generated by the evaluation result. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 11 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Pin arrangement ■ Figure 1.1.3 Pin Arrangement (TOP VIEW) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 12 The absolute maximum ratings are the limit values applied to the chip, which do not lead to damage. They shall not guarantee proper operation. Note: Connect bypath ceramic capacitance (0.1 μF or more) between all of power supply pins and GND nearby these pins. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 13 AVDDPL,AVDDSD AVDDC = 1.8V AVDDC 16.6 28.5 VDDIO = 1.8V VDD = 1.2V DVDD current VDD33 Measured by tester of Panasonic VDDIO current 26.6 32.2 VDD18,VDD18L VDD current 121.7 186.0 (Note) The standard current value is a reference value of “FULL SCAN 12bit mode” in the Industrial Devices Company mounting environment.

  • Page 14: Electrical Characteristics

    Note) Only the terminal that must be controlled during normal operation has been described. Refer to Table 1.1.2 (List of Pin Descriptions, Process and Functions No.1) and Table 1.1.3(List of Pin Descriptions, Process and Functions No.2) for the test pins processing. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 15: Ac Characteristics

    Min. Max. Unit VD “H“period Tvdh Vcycle-10T MCLK HD “H“period Thdh Hcycle-10T MCLK Vcycle : Scan cycle of vertical synchronous signal Hcycle : Scan cycle of horizontal synchronous signal 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 16 MCLK Figure 1.2.2.1-4 Definition of MCLK input timing specifications Table 1.2.4 AC characteristics of MCLK input signal (Reference design) Parameter Symbol Min. Typ. Max. Unit Remarks Clock duty ratio 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 17: Characteristics Of Lvds Output Signal (Reference Design)

    /SDOD  M Figure 1.2.2.2-3 Definition of output variation and Different skew of LVDS output (SDOD) SDOD2P/M SDOD5P/M (Differntial signaling) SDOD8P/M Figure 1.2.2.2-4 Definition of output duty ratio of LVDS clock 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 18 Figure 1.2.2.2-5 Definition of AC Characteristics of LVDS Output Signal Note : The figure of “0~9” or the character of “A” enters for “”, and it becomes specifications of all LVDS pins. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 19: Imaging Characteristics

    Measure at Analog gain = 3.94dB for parameters without a note. [ The other testing parameters ] ・Transient area : no line defect of white or black in the standard illuminance. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 20: Register Setting For Test

    0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0024 0000 0000 0000 0000 0000 0E29 0000 0000 0000 0000 0E0B 0000 000A 0000 0000 0000 0E0C 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 21: Spectral Characteristics

    Until : Indefinite 1.3.3 Spectral Characteristics Spectral characteristics are described below. (Reference value) 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 Wavelength [nm] Figure 1.3.1 Spectral Characteristics 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 22: Test Methods Of Imaging Characteristics

    Definition of the accumulation time "1/30 seconds" mode. ■ Accumulation time is 1/30 seconds. Everything else is the same setting as the standard imaging state. The light source is shielded. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 23: Defects In The Dark Condition

    Modulation defects contrast(%)=((defects:subtracted image) / (individual color channel sensitivity))×100 *2 : Modulation defects is determined the count of single defects and adjacent defects. 4712 Measurement area 3488 3590 4632 Figure 1.4.2 Measurement area of modulation defects 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 24: Saturated Output

    R / Gr sensitivity ratio = ( Red channel sensitivity ) / ( Green : Gr channel sensitivity ) B / Gb sensitivity ratio = ( Blue channel sensitivity ) / ( Green : Gb channel sensitivity ) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 25: Average Dark Signal

    1 second. And calculate the OB level difference at the accumulation time of 2 seconds from the result and the difference of 1/16.25 seconds and 1 second. 4712 OB area Measurement area 3488 3590 3512 4632 Figure 1.4.6 Measurement area of the OB level difference 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 26: Dark Signal Shading

    D1=A(1) - DR(1) DR(1) A(1) ・ DR(2) A(2) ・ 3590 3487 ： ・ DR(8) A(9) DR(9) A(10) D10=A(10) - DR(10) 4620 Figure 1.4.8 Measurement area of vertical dark signal shading 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 27: Luminance Shading

    Chroma = max ( SQRT ( CRx * CRx + CBx * CBx ) ) Hue = SQRT ((CBmax - CBmin)*(CBmax - CBmin) + (CRmax - CRmin)*(CRmax - CRmin)) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 28: Defect Standard

    Allowance count 517.9 LSB < X Count the adjacent defects over 517.9 LSB. See "1.4.1 Defects in the dark condition" of page 21 for the area of counting defects. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 29: Modulation Defects Standard

    Determine the total of dark defects, modulation white defects, and modulation black defects. Treat as fail devices when defect counts are over allowable standard into the following formula. nDW＋nB1＋nB2＋nW1＋nW2 ≦ 1024 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 30: Adjacent Defect Judgment

    2) White defects and black defects are judged as the adjacent separately. ( ex. Even if white and black defect is adjacent, these do not count as adjacent defects. ) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 31: Examples Of Pixel Defect

    MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite 1.5.4 Examples of pixel defect :Defect pixel over the threshold :Adjacent same color pixel 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 32: Driving Condition

    Table 1.6.1 Data format of Send (Write) Mode 1byte 2byte 3byte 4byte Write Address lower 8bit Address upper 7bit Data lower 8bit (IO) Data upper 8bit(IO) mode + write control 1bit 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 33: Send (Write) Timing For Register

    From the “last-SCK input” to the “SCS rising edge”. tSCS2 tSCW 28.57 10000 SCK cycle (100 kHz ~35 MHz) tSST Serial I/F SETUP-time for SCK tSHD Serial I/F HOLD-time for SCK 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 34 28.57 10000 SCK cycle (100 kHz ~ 35 MHz) tSST Serial I/F SETUP-time for SCK tSHD Serial I/F HOLD-time for SCK ※r_clkrst = Reset of CKG (adr:0x0000[4]) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 35 3byte 4byte 3byte 4byte Address(n) data data data Writing starting Data of Data of address address(n) address(n+1) Figure 1.6.1.1-4 Timing for Consecutive Writing ※r_clkrst = Reset of CKG (adr:0x0000[4]) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 36: Timing For Consecutive Writing

    Data output Blanking Data output Internal-VD Figure 1.6.2-1 Timing of register writing Note : The timing chart since this chapter is described by VD falling edge and HD rising edge. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 37 Reflection timing writing update (latch) (Type1) (Type2) Figure 1.6.2-2 Update timing for Register Setting Note : Please refer to the Register Specifications for the Update timing of each register. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 38: Operation Sequence

    Note : Please defend the order of turning on the power supply of VDD18, VDD12 and VDD33. Follow the reverse procedure of start-up sequence to shut down the power supply. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 39: Initialize Sequence

    For more information about this limitation, please refer to “[Note] When 5 times or more HD can not be input after canceling TG reset.” in this chapter. Start the imaging. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 40 Stability waiting Register setting Tvchp TG reset release Register setting HD Input(It recommends it five times or more.) HD/VD Input Taking picture beginning Figure 1.6.3.2-1 Flow Chart of initialize sequence 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 41 0.15     Up/Down converter circuit stability waiting Tvchp   LVDS enable time Tpulvds 1.5+α μs ※ α is an internal system delay time (380 ns). 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 42 Value ≧ 4 Don't care(high/low) Don't care(high/low) Internal signal (TG res et regis ter) Figure 1.6.3.2-3 When 5 times or more HD can not be input after canceling TG reset 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 43: Power Save Sequence

    *1 Either of "H" or "L" input is necessary for the MCLK/VD/HD-pin. The operation is no problem even if the clock/the pulse are input, but power consumption of VDD18 increases. Therefore, "H" or "L" input is recommended. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 44 Diffusion process condition : Typical ※2 Return time is a minimum value based on our recommended sequence and calculated at SCK=35MHz. Note : Please supply all power in each power save mode. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 45 CKG-Reset register Power save TG-Reset register mode2 :Low Hcycle or more Tpdlvds Figure 1.6.3.3-1 Timing chart of shift sequence from normal to Power save 1 and Power save 2 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 46 Power save3-1:4'b0001 / Power save3-2:Don't care CKG-Reset register TG-Reset register Hcycle or more Tpdlvds Figure 1.6.3.3-2 Timing chart of shift sequence from normal to Power save 3-1 and Power save 3-2 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 47 Internal signal (Register) Power save register 4'b0010 4'b0011 CKG-Reset register "High" TG-Reset register Tpulvds HD input Figure 1.6.3.3-3 Timing chart of return sequence from Power save 1 to normal 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 48 Internal signal (Register) Power save register 4'b0000 4'b0011 CKG-Reset register TG-Reset register HD input Tpll Tpulvds Figure 1.6.3.3-4 Timing chart of return sequence from Power save 2 to normal 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 49 Internal signal (Register) Power save register 4'b0001 4'b0011 CKG-Reset register TG-Reset register 10T@MCLK Tpll HD input Tvchp Tpulvds Figure 1.6.3.3-5 Timing chart of return sequence from Power save 3-1 to normal 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 50 Internal signal (Register) Power save register 4'b0001 4'b0011 CKG-Reset register TG-Reset register 10T@MCLK Tpll HD input Tvchp Tpulvds Figure 1.6.3.3-6 Timing chart of return sequence from Power save 3-2 to normal 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 51: Operation

    Full scan (16:9) 10bit 29.97 4712 2702 2730 0.34 *1: Since the “port” field is described in total number of ports, number of ports per channel in 2ch-format is 1/2. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 52: Pixel Format In Each Driving Mode

    TR_B 3590 3488 Full scan 10bit Horizontal pixel composition -1ch8port10bit Total H_S1 H_S2 TR_S active TR_E -2ch4port10bit 4712 4632 Vertical pixel composition Total TR_T active TR_B 3590 3488 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 53 TR_T active TR_B 1208 1160 V2/3mix H3mix Horizontal pixel composition -1ch4port10bit Total H_S1 H_S2 TR_S active TR_E -2ch2port10bit 1572 1543 Vertical pixel composition Total TR_T active TR_B 1212 1160 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 54 TR_B 1270 1168 Full scan (16:9) 10bit Horizontal pixel composition -1ch8port10bit Total H_S1 H_S2 TR_S active TR_E -2ch4port10bit 4712 4632 Vertical pixel composition Total TR_T active TR_B 2702 2600 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 55: Output Timing

    Output timing from HD and VD in each Driving Mode are shown in Table 1.7.5 Hcycle H_FRONT H_PIX H_BACK ・ ・ Pixel array ・ ・ ・ ・ Figure 1.7.2.1-1 Output timing chart from HD and VD and number of CYCLE 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 56 Full scan (16:9) 10bit 2730 612 + α 2985 363 - α 2702 0≦α＜6 Note : When the value of H_BACK is minus, pixel data outputs across the following Hcycle. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 57 Typ. Max. Unit LVDS enable time   Tpulvds 1.5+α μs LVDS disable time   Tpdlvds 0.1+α μs ※ α is an internal system delay time (380 ns). 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 58 Blanking Figure 1.7.2.1-3 Data output timing chart (H-cycle) Note : The period of Horizontal-Front-Blanking (H_FRONT) changes because output trigger is internal PLL clock. Therefore, please use the recognition code. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 59: Reading Pixel Format In Each Driving Mode

    V2/2mix H2mix (Mode No.3,No.4,No.5) Gr' = (Gr0_0+Gr2_0) + (Gr0_2+Gr2_2) R' = (R0_1+R2_1) + (R0_3+R2_3) B' = (B1_0+B3_0) + (B1_2+B3_2) Gb' = (Gb1_1+Gb3_1) + (Gb1_3+Gb3_3) Figure 1.7.3-1 Reading pixel format (V2/2mix H2mix) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 60 Gr' = (Gr0_0+Gr2_0+Gr4_0) + (Gr0_2+Gr2_2+Gr4_2) + (Gr0_4+Gr2_4+Gr4_4) R' = (R0_3+R2_3+R4_3) + (R0_5+R2_5+R4_5) + (R0_7+R2_7+R4_7) B' = (B3_0+B5_0+B7_0) + (B3_2+B5_2+B7_2) + (B3_4+B5_4+B7_4) Gb' = (Gb3_3+Gb5_3+Gb7_3) + (Gb3_5+Gb5_5+Gb7_5) + (Gb3_7+Gb5_7+Gb7_7) Figure 1.7.3-2 Reading pixel format (V3/3mix H3mix) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 61 Gr' = (Gr0_0+Gr4_0) + (Gr0_2+Gr4_2) + (Gr0_4+Gr4_4) R' = (R0_3+R4_3) + (R0_5+R4_5) + (R0_7+R4_7) B' = (B3_0+B7_0) + (B3_2+B7_2) + (B3_4+B7_4) Gb' = (Gb3_3+Gb7_3) + (Gb3_5+Gb7_5) + (Gb3_7+Gb7_7) Figure 1.7.3-3 Reading pixel format (V2/3mix H3mix) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 62 Gr' = (Gr0_0+Gr4_0+Gr8_0) + (Gr0_2+Gr4_2+Gr8_2) + (Gr0_4+Gr4_4+Gr8_4) R' = (R0_3+R4_3+R8_3) + (R0_5+R4_5+R8_5) + (R0_7+R4_7+R8_7) B' = (B7_0+B11_0+B15_0) + (B7_2+B11_2+B15_2) + (B7_4+B11_4+B15_4) Gb' = (Gb7_3+Gb11_3+Gb15_3) + (Gb7_5+Gb11_5+Gb15_5) + (Gb7_7+Gb11_7+Gb15_7) Figure 1.7.3-4 Reading pixel format (V3/7mix H3mix) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 63 Gr' = (Gr0_0+Gr4_0+Gr8_0) + (Gr0_2+Gr4_2+Gr8_2) + (Gr0_4+Gr4_4+Gr8_4) R' = (R0_3+R4_3+R8_3) + (R0_5+R4_5+R8_5) + (R0_7+R4_7+R8_7) B' = (B13_0+B17_0+B21_0) + (B13_2+B17_2+B21_2) + (B13_4+B17_4+B21_4) Gb' = (Gb13_3+Gb17_3+Gb21_3) + (Gb13_5+Gb17_5+Gb21_5) + (Gb13_7+Gb17_7+Gb21_7) Figure 1.7.3-5 Reading pixel format (V3/13mix H3mix) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 64: Signal Output Of Each Driving Mode

    Output bit×4 Recognition Code for line start. (Start of Line) Output bit×4 Recognition Code for frame end. (End of Frame) Output bit×4 Recognition Code for line end. (End of Line) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 65: Lvds 1Ch 8Port / 2Ch 4Port Format Output

    SDOD3 SDOD4 SDOD4 SDOD5 SDOD2 SDODA SDODA SDOD9 SDOD9 SDOD7 SDOD7 SDOD6 SDOD6 SDOD8 Note : The character of P/M enters for “”. These are regulations of all LVDS-terminal. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 66 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.2-1 Output Timing for Data and Recognition Code (1ch 8port / 2ch 4port 12bit format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 67 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.2-2 Output Timing for Data and Recognition Code (1ch 8port / 2ch 4port 10bit format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 68: Lvds 1Ch 6Port / 2Ch 3Port Format Output

    SDOD0 SDOD1 SDOD1 SDOD3 SDOD3 SDOD5 SDOD2 SDODA SDODA SDOD9 SDOD9 SDOD7 SDOD7 SDOD8 Note : The character of P/M enters for “”. These are regulations of all LVDS-terminal. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 69 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.3-1 Output Timing for Data and Recognition Code (1ch 6port / 2ch 3port 12bit format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 70 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.3-2 Output Timing for Data and Recognition Code (1ch 6port / 2ch 3port 10bit format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 71: Lvds 1Ch 4Port / 2Ch 2Port Format Output

    Port Pin name SDOD0 SDOD0 SDOD1 SDOD1 SDOD5 SDOD2 SDODA SDODA SDOD9 SDOD9 SDOD8 Note : The character of P/M enters for “”. These are regulations of all LVDS-terminal. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 72 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.4-1 Output Timing for Data and Recognition Code (1ch 4port / 2ch 2port 12bit format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 73 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.4-2 Output Timing for Data and Recognition Code (1ch 4port / 2ch 2port 10bit format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 74: Lvds 1Ch 2Port / 2Ch 1Port Format Output

    2ch 1port Port Pin name Port Pin name SDOD0 SDOD0 SDOD5 SDOD2 SDODA SDODA SDOD8 Note : The character of P/M enters for “”. These are regulations of all LVDS-terminal. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 75 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.5-1 Output Timing for Data and Recognition Code (1ch 2port / 2ch 1port 12it format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 76 MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite Figure 1.7.4.5-2 Output Timing for Data and Recognition Code (1ch 2port / 2ch 1port 10bit format) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 77: Exposure Time Control Of Normal Driving (Reference Design)

    Exposure time Figure 1.7.5.1-1 Normal exposure mode timing Note : The update data after the setting change of exposure time is output with the frame one after another. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 78: Long Time Exposure Mode

    Exposure time Figure 1.7.5.2-1 Long time exposure mode timing Note : The update data after the setting change of exposure time is output with the frame one after another. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 79: Exposure Time Control Of Still Capture (Reference Design)

    The number of frames [VD] for Still mode is the value of "Long Time Exposure Setting - 1" (When the setting of Long Time Exposure is 0 and 1, the number of frames is 0VD.) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 80: Output Timing Chart In Still Capture

    The position can be changed by electronic shutter register Still reset signal High period:5Hcycle *Reference Mechanical shutter "OPEN" "CLOSE" "OPEN" Exposure time Figure 1.7.6.2-2 Timing chart of Still exposure control (Method 1 : Over 1VD exposure) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 81 The position can be changed by electronic shutter register Still reset signal High period:5Hcycle *Reference Mechanical shutter "OPEN" "CLOSE" "OPEN" Exposure time Figure 1.7.6.2-4 Timing chart of Still exposure control (Using “tg_rst2” : Within 1VD exposure) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 82: Cancel Operation Of Long Time Exposure In Still Mode

    Invalid Data (Dummy output invalid) Output Internal signal Internal-VD Still reset signal *Reference Mechanical shutter "OPEN" "CLOSE" "OPEN" Exposure time Figure 1.7.6.3-1 Cancel operation chart of Long Exposure timing 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 83: Sequence Of Driving Mode Transition (Reference Design)

    (Over 5times HD) address:0x0043 address:0x0031 address:0x0053 address:0x0032 address:0x0060 HD/VD input address:0x0034 address:0x0064 address:0x0000 address:0x0068 address:0x0074 address:0x007B Taking picture address:0x007C biginning address:0x007F Figure 1.7.7 Flow chart of changing the driving mode 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 84: Signal Output Timing Of Driving Mode Transition (Reference Design)

    Extract position change Extract positin register writing update data LVDS Data output Blanking Data output Blanking Data output Internal-VD Figure 1.7.9 Timing chart of changing the extract position 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 85: Gain Control (Reference Design)

    Total Gain 23.9dB Digital Gain -12.0dB Analog Gain -42dB Register value Analog 128～ 511 Gain Register value Digital 0～ 319 321～ 575 Gain Figure 1.7.10 Recommended Gain Assignment (Tentative) 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 86: Reference Circuit

    SDODAP ch1 port10 SDODAM VD input/output HD input/output Power save control Analog GND 1.8V I/F Digital GND Serial I/F Master clock (54MHz) Figure 1.7.11-1 Reference circuit for 1ch8port format 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 87 SDODAP ch2 port1 SDODAM VD input/output HD input/output Power save control Analog GND 1.8V I/F Digital GND Serial I/F Master clock (54MHz) Figure 1.7.11-2 Reference circuit for 2ch4port format 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 88 -Since the decoupling capacitor inserted in the power supply is a reference value and different according to the board of Set, It should be optimize. -All terminals of power supply and GND in sensor should be processed. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 89: Package

    MN34120PAJ Confidential Specifications Total Page Page Until : Indefinite 1.8 Package 1.8.1 Dimensions (H, V) = (+0.32, +0.01) mm 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 90: Marking Specifications

    [1] Product number 34120PA [2] ID number A123456 78901B3 Indication item Indication Description contents Product type 34120PA MN34120PA series ID number 14 characters * UTAC: UTAC Manufacturing Services Singapore Pte. Ltd. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 91: Packing Specification

    (At the end of a lot, empty trays may be used to make up the six trays packed in the aluminum pack.) *: Place silica gel on taped tray, put the tray into an aluminum pack and seal the pack with an aluminum laminator. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 92 ・ Case of one Aluminum pack Spacer D-label Aluminum pack (one pack) Aluminum packs （ two packs ） Product name (C-3) label Packing case (Product name, quantity, shipping date) Packing case 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 93: Notes On Device Handling

    (11) Only use containers that are not subject to static electric changes, such as conductive containers or containers that have had an antistatic treatment applied, to transport MOS sensors or circuit boards containing MOS sensors. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 94 The heat generated may make the MOS sensor inoperative. (5) Don't input the pulse without power supply. (6) Startup of MOS sensor, please refer to 1.6.3.1 Power on Sequence. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 95 If automatic solder suction machine is used, please use the antistatic machine with temperature control function. Also, please ground a vacuum pump to prevent surge from a motor. (5) Cautions This product is lead-free. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 96 (3) As time passes, MOS sensors are subject to the sudden occurrence of white defects due to cosmic rays. Please correct these white defects by the defects correction method. 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.
  • Page 97 168 h Packing : 168 ~ 336 h d) If you plan to store MOS sensor longer than 336h, please vacuum pack again (Silica gel packed with. ). 2015/10/01 Generalplus Technology Inc. Enactment Revision Panasonic Semiconductor Solutions Co., Ltd.

  • Page 98: Guarantee For Mos Type Image Sensor

    1.10.2 Guarantee for MOS type Image Sensor 1) Panasonic guarantees MOS sensor devices in the case of the following contents are filled. (1) MOS sensor has been using under the conditions described in “ 1.10 Notes on Device Handling ”.
  • Page 99 Panasonic Semiconductor Solutions Co., Ltd. 1 Kotari-yakemachi, Nagaokakyo City, Kyoto 617-8520, Japan Tel:075-951-8151...

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