Panasonic MN34120PAJ Manual page 9

Confidential
Until : Indefinite
Pins
■
The descriptions and the functions of the pins are as follows.
Table 1.1.2 List of Pin Descriptions, Process and Functions No.1
Management
PIN No. Pin name
No
1 A3 SDOD0P LVDS出 力 (port00 data + )
2 A4 SDOD2P LVDS出 力 （ 2ch mode: ch1 clock +)
3 A5 GND
4 A6 VDD
5 A7 MCLK
6 A8 HD
7 A9 VDD18
SDOD0M LVDS output (port00 data -)
8 B3
9 B4 SDOD2M LVDS output (2ch mode: ch1 clock -)
10 B5 GND
11 B6 VDD
12 B7 SCS
13 B8 VD
14 B9 SCK
15 C1 SDOD1M LVDS output (port01 data -)
SDOD1P LVDS output (port01 data +)
16 C2
SDOD4P LVDS output (port03 data +)
17 C3
18 C4 VRES
19 C5 TM
20 C6 PSV
21 C7 TESTIO
22 C8 SI
23 C9 AGNDPL
24 C10 AVDDC
25 C11 AVDDC
SDOD3M LVDS output (port02 data -)
26 D1
SDOD3P LVDS output (port02 data +)
27 D2
SDOD4M LVDS output (port03 data -)
28 D3
29 D9 AGNDC
30 D10 AGNDC
31 D11 CAPD1
32 E1 SDOD5M LVDS output (1ch mode: clock -)
33 E2 SDOD5P LVDS outpu (1ch mode: clock +)
34 E3 GND
35 E9 AGNDP
36 E10 AGNDP
37 E11 AGNDR
38 F1 SDOD6M LVDS output (port13 data -)
39 F2 SDOD6P LVDS output (port13 data +)
2015/10/01
Enactment Revision
Specifications
Description
Digital GND
Digital 1.2V power supply
Master clock
Horizontal standard pulse I/O
Digital 1.8V power supply
Digital GND
Digital 1.2V power supply
Serial chip select
Vertical standard pulse I/O
Serial clock
Resistance for internal voltage
Digital test terminal
Power save terminal
Analog test terminal
Serial data input
Analog GND
Analog 1.8V power supply
Analog 1.8V power supply
Analog GND
Analog GND
External capacity terminal
Digital GND
Analog GND
Analog GND
Analog GND
I/O
O Zdiff=100Ω(under ±1%)
O Zdiff=100Ω(under ±1%)
G
P Decoupling capacity (2.2μF) is arranged between GND.
I Master clock input terminal 54MHz
IO Horizontal standard pulse I/O. Slave mode: input, Master mode: output
P Decoupling capacity (2.2μF) is arranged between GND.
O Zdiff=100Ω(under ±1%)
O Zdiff=100Ω(under ±1%)
G
P Decoupling capacity (2.2μF) is arranged between GND.
I
IO Vertical standard pulse I/O. Slave mode: input, Master mode: output
I
O
Zdiff=100Ω(under ±1%)
O
O Zdiff=100Ω(under ±1%)
O open
I Connect GND
I Low: Power save, High: At operation
IO open
I
G
P Decoupling capacity (2.2μF) is arranged between AGNDC.
P Decoupling capacity (2.2μF) is arranged between AGNDC.
O
Zdiff=100Ω(under ±1%)
O
O Zdiff=100Ω(under ±1%)
G
G
IO Connect 2.2μF capacitance between AGNDR ※ 2
O
Zdiff=100Ω(under ±1%)
O
G
G
G
G
O
Zdiff=100Ω(under ±1%)
O
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
Total Page
Page
7
96
Processing