Panasonic MN34120PAJ Manual page 48

Confidential
Until : Indefinite
Return sequence from Power save 2
■
Return sequence from power save 2 to normal is as follows.
(1) Power save register (0x000E[3:0]) writing
(The power save is canceled by the rising edge of the SCS-pin.)
PLL oscillation stability waiting
(2) CKG reset register (0x0000[4]) writing:"H" ⇒ "L"
Up/Down converter circuit register (0x0005[2:1]) writing: " 2'b10" ⇒ " 2'b00"
TG reset register (0x0000[8]) writing: "L" ⇒ "H"
- HD input beginning
- VD input timing waiting (wait over 5HD-input)
(3) VD/HD Input
External pin
PSV
MCLK
SCK
SI
SCS
VD
HD
LVDS
Internal signal (Register)
Power save register
CKG-Reset register
TG-Reset register
Figure 1.6.3.3-4 Timing chart of return sequence from Power save 2 to normal
2015/10/01
Enactment Revision
Specifications
"High"
Don't care(High/Low)
Don't care(High/Low)
4'b0000
(1) (2) (3)
Tpll
Tpulvds
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
Total Page
Page
46
96
Blanking
4'b0011
HD input