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Confidential
Until : Indefinite
Timing Chart (Initialize Sequence)
■
Power
PSV
MCLK
SCK
SI
SCS
PSV release waiting
: Tpsv
MCLK input waiting : Tmclk
PLLREG setting time
PLL oscillation stability waiting : Tpll
VD
HD
LVDS
Parameter
PSV release waiting
MCLK input waiting
PLL oscillation stability waiting
Up/Down converter circuit stability waiting
LVDS enable time
※ α is an internal system delay time (380 ns).
2015/10/01
Enactment
Revision
Specifications
Up/Down converter circuit
Stability waiting : Tvchp
circuit of dividing frequency and
Up/Down converter circuit reset release
Don't care(high/low)
Don't care(high/low)
Figure 1.6.3.2-2 Timing chart of Initialization
Table 1.6.8 Initialization timing
Symbol
Tpsv
Tmclk
Tpll
Tvchp
Tpulvds
Generalplus Technology Inc.
MN34120PAJ
Total Page
TG reset release
HD Input (It recommends it five times or more)
Blanking
LVDS enable tim e : Tpulvds
Min.
Typ.
10T
1.0
0.15
30
1.5+α
Panasonic Semiconductor Solutions Co., Ltd.
Page
39
96
Data output
BLK
Max.
Unit
MCLK
μs
ms
ms
μs
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