Panasonic MN34120PAJ Manual page 34

Confidential
Until : Indefinite
Register Other Than PLLREG Register (Address: except 0x0000 to 0x0011)
■
The access becomes "registers other than the PLLREG register" with possible at "PLLREG registers
r_clkrst=High".
r_clkrst
SCS
SCK
SI A0
tRST tSCS0
Figure 1.6.1.1-2 Definition of Send timing for excluding PLLREG register (Write)
Table 1.6.3 AC Characteristics of Send Timing for excluding PLLREG Register (Reference design)
Parameter Min.
tRST
60
tSCS0 30
tSCS1 30
tSCS2 60
tSCW 28.57
tSST 5
tSHD 5
※r_clkrst = Reset of CKG (adr:0x0000[4])
2015/10/01
Enactment Revision
Specifications
A1 A2 A13 A14 Low
tSCW tSST tSHD
Typ. Max. Unit
ns
- -
- - ns
- - ns
- - ns
- 10000 ns
- - ns
- - ns
D0 D1 D7 D8 D9
Remarks
From the internal reset release (r_clkrst=High) to "SCS
= Low".
From "SCS=Low" to the "SCK input".
-
-
SCK cycle (100 kHz ~ 35 MHz)
Serial I/F SETUP-time for SCK
Serial I/F HOLD-time for SCK
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
Total Page
Page
32
96
D14 D15
tSCS1 tSCS2