Panasonic MN34120PAJ Manual page 40

Confidential
Until : Indefinite
Flow Chart of initialize sequence
■
PSV-pin L⇒H
MCLK input
Up/Down converter circuit
Register setting
Row circuit power save release
Register setting
PLL and circuit of dividing frequency
register setting
Other PLLREG register setting
PLL oscillation stability waiting
Reset release of internal clock
Register setting
Up/Down converter circuit Reset release
Register setting
Up/Down converter circuit
Stability waiting
TG reset release
Register setting
HD Input(It recommends it five
times or more.)
HD/VD Input
Taking picture beginning
2015/10/01
Enactment Revision
Specifications
Power ON
Wait over 10T(@MCLK)
Wait over 1μsec
Tpll
Tvchp
Figure 1.6.3.2-1 Flow Chart of initialize sequence
※Please note that the register other than PLLREG
can not be written normally when the waiting time for
PLL oscillation stability is not enough.
※If the waiting time for Up/Down converter
circuit stability is missing, normal image would
not be achieved.
Registers other than PLLREG
Register setting
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
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