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Confidential
Until : Indefinite
No
Mode
1
Full scan 12bit
2
Full scan 10bit
3
V2/2mix H2mix
4
V2/2mix_c H2mix
5
V2/2mix_c H2mix
6
V3/3mix H3mix
7
V2/3mix H3mix
8
V2/3mix_c H3mix
9
V3/7mix H3mix
10
V3/13mix H3mix
Full scan
11
5 division output
12
Full scan (16:9) 10bit
0≦α＜6
Note :
When the value of H_BACK is minus, pixel data outputs across the following Hcycle.
2015/10/01
Enactment
Revision
Specifications
Table 1.7.5 Data output timing in each Driving Mode
Out
Hcycl
Vcycl
put
e
e
Bit
(mclk)
(line)
12
918
3620
10
666
3632
12
792
2275
650
1386
12
/750
/1440
630
1430
10
/750
/1440
12
1638
1226
10
630
1430
630
1430
12
/720
/1500
630
715
12
/1260
/715
/1260
/1430
10
558
344
10
660
1365
10
660
2730
H_PIX
(LVDS CLK / 324MHz)
H_FRONT
H_PIX
H_BACK
712 + α
3582
1214 - α
612 + α
2985
760 + α
3582
550 + α
2412
/ 1538 - α
1243 - α
507 + α
2030
/ 1963 - α
586 + α
2406
6836 - α
507 + α
2005
1268 - α
586 + α
2406
/ 1328 - α
586 + α
2406
/ 4568 - α
/ 4568 - α
502 + α
2005
612 + α
2985
612 + α
2985
Generalplus Technology Inc.
Panasonic Semiconductor Solutions Co., Ltd.
MN34120PAJ
Total Page
Page
54
96
V_PIX
(Hcycle)
V
F
R
V_PIX
O
N
T
1
3590
399 - α
1
3590
410 - α
1
1804
938 - α
1
1366
1
1366
1
1208
1
1212
788 - α
1
924
788 - α
1
544
841 - α
1
310
363 - α
1
1270
363 - α
1
2702
V_B
ACK
29
41
470
19
/ 73
63
/ 73
17
217
505
/575
170
/170
/885
33
94
27
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