Board Specifications - AMD Xilinx ZCU670 User Manual

The ZCU670 provides a rapid prototyping platform that uses the XCZU67DR-2FSVE1156I
device. The ZU67DR contains many useful processor system (PS) hard block peripherals exposed
through the multi-use I/O (MIO) interface and a variety of FPGA programmable logic. The
following table lists a brief summary of the resources available within the ZU67DR.
Feature set overview, description, and ordering information is provided in the Zynq UltraScale+
RFSoC DFE Data Sheet: Overview (DS883).
Table 1: Zynq UltraScale+ RFSoC ZU67DR Features and Resources
Digital front end
14-bit 2.95 GSPS RF-ADC with DDC
14-bit 5.9 GSPS ADC RF-DAC with DDC
14-bit 10 GSPS RF-DAC with DUC
APU: Quad-core Arm
RTPU: Dual-core Arm Cortex-R5F MPCore with CoreSight
HD I/O
HP I/O
MIO banks
PS GTR 6 Gb/s transceivers
PL GTY 28 Gb/s transceivers
System logic cells
CLB flip-flops
CLB LUTs
Maximum distributed RAM (Mb)
Block RAM blocks
UltraRAM blocks
DSP slices
100G Ethernet with RS-FEC

Board Specifications

Dimensions
Height: 12.225 inches (31.05 cm)
Width: 10.675 inches (27.11 cm)
Thickness: 0.122 inches (0.310 cm)
Note: A 3D model of this board is not available.
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
Feature
® Cortex ® -A53 MPCore with CoreSight™
Chapter 1: Introduction
Resource Count
Included
8
2
8
1
1
96
312
3 banks, total of 78 pins
4 PS-GTRs
8 GTYs
489,300
447,360
223,680
6.9
648
160
1,872
1
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