AMD Xilinx ZCU670 User Manual page 53

GTY Transceivers
The GTY transceivers in the ZU67DR are grouped into two channels or quads. The reference
clock for a quad can be sourced from the quad above or the quad below the GTY quad of
interest. The two GTY quads used on the ZCU670 board have the connectivity listed below. The
following table shows the MGTY assignments.
Table 21: ZCU670 ZU67DR GTY Mapping
ZU67DR-FSVE1156
zSFP+
Four MGTs are provided by PL-side MGT banks 127 and 128 for the quad (2x2 connector) zSFP+
interface. Available GTY reference clocks include two sets of clocks to/from IDT 8A34001 U409.
Each zSFP+ connector provides an I2C based control interface. This I2C interface is accessible for
each individual zSFP+ module through the I2C multiplexer topology on the ZCU670.
For additional information on GTY transceivers, see the UltraScale Architecture GTY Transceivers
User Guide (UG578).
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU670 board XDC file, referenced in
PS GTR Transceivers
The PS-side GTR transceiver Bank 505 supports USB (3.0). The remainder of the GTR
transceivers are connected to the FMC+ connector.
Bank 505 USB0 lane 2 supports the USB0 (USB3.0) interface described in
and USB 2.0 ULPI
See Appendix A: VITA57.4 FMCP Connector
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
ZCU670 ZU67DR-FSVE1156 GTY Mapping
SFP3
SFP2
SFP1
SFP0
USER_MGT_REFCLK
8A34001_CLK1
FMCP_HSPC_DP3
FMCP_HSPC_DP2
FMCP_HSPC_DP1
FMCP_HSPC_DP0
8A34001_Q11_OUT
8A34001_CLK2_IN
Appendix B: Xilinx Design
PHY. The PS-side GTR transceiver provides USB 3.0 host-only connectivity.
Chapter 3: Board Component Descriptions
Constraints.
Pinout.
Send Feedback
ch3
ch2
ch1
GTY Quad 127
ch0
refclk1
refclk0
ch3
ch2
ch1
GTY Quad 128
ch0
refclk1
refclk0
USB 3.0 Transceiver
www.xilinx.com
53