AMD Xilinx ZCU670 User Manual page 22

The Zynq UltraScale+ RFSoC PS block has three major processing units:
• Cortex-A53 application processing unit (APU) Arm v8 architecture-based 64-bit quad-core
multiprocessing CPU.
• Cortex-R5F real-time processing unit (RPU) Arm v7 architecture-based 32-bit dual RPU with
dedicated tightly-coupled memory (TCM).
• Mali-400 graphics processing unit (GPU) with pixel and geometry processor and 64 KB L2
cache.
The Zynq UltraScale+ RFSoC PS has four high-speed serial I/O (HSSIO) interfaces supporting the
following protocols:
• Integrated block for PCI Express
• SATA 3.1 specification compliant interface.
• USB 3.0 interface-compliant to USB 3.0 specification implementing a 5 Gb/s line rate.
• Serial GMII interface-supports a 1 Gb/s SGMII interface.
The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate
user-created hardware accelerators and other functions in the PL logic that are accessible to the
processors. They can also access memory resources in the processing system. The PS I/O
peripherals, including the static/flash memory interfaces share a multiplexed I/O (MIO) of up to
78 MIO pins. Zynq UltraScale+ RFSoCs can also use the I/O in the PL domain for many of the PS
I/O peripherals. This is done through an extended multiplexed I/O interface (EMIO) and boots at
power-up or reset.
The ZCU670 is an evaluation board featuring the ZU67DR Zynq UltraScale+ RFSoC DFE device.
This board enables the evaluation of applications requiring multi-band (sub-7 GHz, mmWave),
multi-std (5G, LTE, etc.), and multi-mode (TDD, FDD) radios, including Milcom and Satcom
applications. The ZCU670 board is equipped with all the common board-level features needed
for design development, such as DDR4 memory, networking interfaces, an FMC+ expansion port,
as well as access to the RFMC 2.0 interface.
The ZU67DR includes not only the direct RF sampling converters but also a fully dedicated
digital front-end (DFE) subsystem with all the required signal processing blocks. With this
dedicated IP, the ZCU670 enables ~50% lower power (at 500 MHz) versus equivalent soft IP
implementation. The DFE blocks implement the key wireless DFE logic in dedicated blocks and
has multiple instances placed within the programmable logic fabric. Each dedicated IP block can
be bypassed and appended for maximum flexibility and customization.
The following figure shows the Zynq UltraScale+ RFSoC DFE block diagram.
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
Chapter 3: Board Component Descriptions
interface-PCIe base specification version 2.1 compliant.
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