AMD Xilinx ZCU670 User Manual page 44

Table 18: Clock Connections to ZU67DR U1 (cont'd)
Clock Source Ref. Des. and
Pin
U43.38
U43.37
U43.42
U43.41
U43.45
U43.44
U43.51
U43.50
U43.54
ADC_CLK_226
J8 (P) SMA CONN.
J98 (N) SMA CONN.
DAC_CLK_228
J99 (P) SMA CONN.
J100 (N) SMA CONN.
U409 8A34001 eCPRI Clock
U409.A9 (Q1)
U409.B9 (Q1)
U409.A11 (Q2)
U409.B11 (Q2)
U409.A12 (Q3)
U409.B12 (Q3)
U409.M8 (Q7)
U409.L8 (Q7)
U409.A6 (Q8)
U409.B6 (Q8)
U409.M6 (Q11)
U409.L6 (Q11)
Notes:
1. U1 ZU67DR Bank 503 supports LVCMOS18 level inputs.
2. Series capacitor coupled, U1 MGT (I/O standards do not apply).
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
Net Name
SI5381_GTR_REF_CLK_P
SI5381_GTR_REF_CLK_N
SI5381_PL_CLK_P
SI5381_PL_CLK_N
SI5381_GTR_REFCLK_USB3_P
SI5381_GTR_REFCLK_USB3_N
SI5381_CLK_125_P
SI5381_CLK_125_N
SI5381_SMA_SE (undefined on schematic)
ADC_CLK_226_P
ADC_CLK_226_N
DAC_CLK_228_P
DAC_CLK_228_N
8A34001_Q1_OUT_P
8A34001_Q1_OUT_N
8A34001_Q2_OUT_P
8A34001_Q2_OUT_N
8A34001_Q3_OUT_P
8A34001_Q3_OUT_N
8A34001_Q7_OUT_P
8A34001_Q7_OUT_N
8A34001_Q8_OUT_P
8A34001_Q8_OUT_N
8A34001_Q11_OUT_P
8A34001_Q11_OUT_N
Chapter 3: Board Component Descriptions
I/O Standard
2
2
LVDS
LVDS
2
2
LVDS
LVDS
LVCMOS
See Zynq UltraScale+ RFSoC Data Sheet:
DC and AC Switching Characteristics
(DS926)
See Zynq UltraScale+ RFSoC Data Sheet:
DC and AC Switching Characteristics
(DS926)
See Zynq UltraScale+ RFSoC Data Sheet:
DC and AC Switching Characteristics
(DS926)
See Zynq UltraScale+ RFSoC Data Sheet:
DC and AC Switching Characteristics
(DS926)
2
2
LVDS
LVDS
LVDS
LVDS
2
2
LVDS
LVDS
2
2
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