AMD Xilinx ZCU670 User Manual page 55

See the FPGA Mezzanine Card (FMC) VITA 57.4 specification on the
Alliance website for additional information on the FMCP HSPC connector.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU670 board XDC file, referenced in
Cooling Fan Connector
[Figure 2, near callout 33]
The ZCU670 uses the Infineon MAX6643 (U50) fan controller, which autonomously controls the
fan speed by controlling the pulse width modulation (PWM) signal to the fan based on the die
temperature sensed via the FPGA's DXP and DXN pins. The fan rotates slowly (acoustically quiet)
when the RFSoC is cool and rotates faster as the FPGA heats up (acoustically noisy). The fan
speed (PWM) versus the RFSoC die temperature algorithm along with the over temperature set
point and fan failure alarm mechanisms are defined by the strapping resistors on the MAX6643
device. The over temperature and fan failures alarms can be monitored by any available
processor in the RFSoC by polling the I2C expander U15 on the I2C0 bus. See the MAX6643
data sheet on the
implementation on this board.
The ZCU670 cooling fan circuit is shown in the following figure.
Note: At initial power on, it is normal for the fan controller to energize at full speed for a few seconds.
VADJ_FMC Power Rail
The ZCU670 evaluation board implements the ANSI/VITA 57.1 section 5.5.1 IPMI support
functionality. The power control of the VADJ_FMC power rail is managed by the U38 system
controller. This rail powers the FMCP HSPC (J28) VADJ pins, as well as the ZU67DR HP banks 66
and 67. The valid values of the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V.
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
Appendix B: Xilinx Design
Maxim Integrated Circuits
Figure 19: ZCU670 Cooling Fan Circuit
Chapter 3: Board Component Descriptions
Constraints.
website for more information on the device circuit
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