AMD Xilinx ZCU670 User Manual page 28

• Data rate: Various depending on Single/Dual/Quad mode
The configuration and Quad-SPI section of the Zynq UltraScale+ Device Technical Reference Manual
(UG1085) provides details on using the Quad-SPI flash memory. For more QSPI details, see the
Micron MT25QU02GCBB8E12-0SIT data sheet on the
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU670 board XDC file, referenced in
GPIO (MIO 13, 38)
These two GPIO bits are connected to the U38 MSP430 system controller for general purpose
signaling or communications between the Zynq UltraScale+ RFSoC and the MSP430 system
controller. These signals are level-shifted by TXS0108E U37. The connections between the U38
system controller and the ZU67DR RFSoC are listed in following table.
Table 8: System Controller U38 GPIO Connections to
ZU67DR U1
Net Name
MIO38_PS_GPIO1
MIO13_PS_GPIO2
I2C Bus Topology Overview
I2C0 (MIO 14-15), I2C1 (MIO 16-17)
The following figure shows a high-level view of the I2C0 and I2C1 bus connectivity.
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
Chapter 3: Board Component Descriptions
Micron Technology
Appendix B: Xilinx Design
MSP430 U38
Pin Name
P1_6
P1_7
website.
Constraints.
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